Memory organization

Details Memory organization Memory organization

1978-08-07

1980-02-19

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

For complementary information

307238, 365156, 365188, G11C 1140

Patent

active

041897820

ABSTRACT:
An improved READ/WRITE circuit for a memory array of cells arranged in rows and columns, where each cell is coupled to a bit line via the conduction path of a single gating transistor which conducts in the source follower mode for one binary condition. The circuit includes a voltage multiplying circuit having an output at which is selectively produced either a read voltage, or a write voltage of significantly greater amplitude than the read voltage. The output of the voltage multiplying circuit is coupled via a level shifting decoder circuit, which passes either the read or the write voltage, to the control electrodes of selected gating transistors. The read voltage applied to the control electrode of a gating transistor turns it on just enough to enable the non-destructive-readout (NDRO) of the contents of its associated memory cell. The application of the write voltage to the control electrode of a gating transistor overdrives it into conduction, enabling information to be easily and safely written into its associated memory cell even at low power supply voltages.

REFERENCES:
patent: 4063225 (1977-12-01), Stewart

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