Memory modules and packages using different orientations and...

Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Assembly of plural semiconductive substrates each possessing...

Reexamination Certificate

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Details

C257S723000, C257S724000, C365S051000, C365S063000, C710S001000

Reexamination Certificate

active

06632705

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to memory modules and packaging of integrated memory circuits.
2. Description of the Related Art
Fast computer systems have needed memory modules and dynamic random access memories (DRAMs) having high bandwidths and short access times. To meet these needs, synchronous DRAM (SDRAM), double data rate SDRAM, and Rambus DRAM (RDD) have been developed. When using RDDs in a main memory, each RDD is generally mounted on a Rambus inline memory module (RiMM).
FIG. 1
shows the configuration of a typical RDD memory system, which includes multiple RiMMs connected to a controller. Each RiMM includes a printed circuit board SUB, on or through which multiple RDDs serially connect to each other. RDDs of each RiMM operate according to signals synchronized with a clock signal. In particular, each RDD of the main memory operates according to a packet of signals, which are sequentially received during a specific period, and each RDD receives and outputs data independently of the other RDDs.
FIG. 2
illustrates a RiMM such as used in the memory system of FIG.
1
. The RiMM includes eight RDDs ID
0
to ID
7
, each of which has sixteen data input/output (I/O) pins (DQ pins) DQA
1
to DQA
8
and DQB
1
and DQB
8
. The bandwidth of the RiMM depends on the output speed and the number of DQ pins or terminals on each RDD. Each RDD ID
0
to ID
7
in
FIG. 2
can be a 8M×16 RDD package.
FIG. 3
is an expanded view of area (A) of FIG.
2
and illustrates how buses on the RiMM connect to the data and control pins of the separate RDD packages.
A pair of RDD packages, for example, RDD ID
0
and RDD ID
1
form a memory having a 16M×16 organization. However, a specific memory organization such as 16M×16 can be achieved in different manners, for example, using two (8M×16) RDD packages or two (16M×8) RDD packages. However, packages for memory chips having different data widths often have different sizes. For example, a packaged for ×8 RDD is typically smaller than a package for a ×16 RDD because the ×8 package has fewer data pins. Accordingly, methods, modules, and packages that use memory chips having narrower data widths to achieve a high data bandwidth facilitate reducing the size of memory components.
SUMMARY OF THE INVENTION
The present invention provides memory modules and methods of packaging memory devices. In accordance with an embodiment of the invention, a method includes: preparing semiconductor packages of the memory devices, each of which has external pins that include external data I/O pins and command signal pins; mounting the packages on a printed circuit board, on which a first bus, a second bus, and a third bus are formed; connecting the data I/O pins of odd-numbered packages to the first bus; connecting the data I/O pins of even-numbered packages to the second bus; and connecting the command signal pins of the packages to the third bus. The semiconductor packages can have orientations that alternate so that even-numbered packages have one orientation and odd-numbered packages have another orientation.
In accordance with another embodiment of the invention, a memory module includes: a printed circuit board on which a first bus, a second bus, and a third bus are formed; and semiconductor packages, each of which includes a memory device, data pins, and command signal pins. In odd-numbered packages, the data pins connect to the first bus, and in even-numbered packages, the data pins connect to the second bus. The command signal pins of the packages connect to the third bus. The even-numbered packages can have orientations or assignment of pins that differ from those of the odd-numbered packages.


REFERENCES:
patent: 5860080 (1999-01-01), James et al.
patent: 5941447 (1999-08-01), Chu et al.
patent: 5996880 (1999-12-01), Chu et al.

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