Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
2011-07-19
2011-07-19
Lamarre, Guy J (Department: 2112)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C365S051000, C365S063000, C365S221000
Reexamination Certificate
active
07984355
ABSTRACT:
A memory module includes a plurality of memory devices and a stacked error correction code memory device. The plurality of memory devices includes one or more memory chips arranged in a plurality of ranks. The stacked error correction code memory device includes a plurality of error correction code memory chips. The number of error correction code memory chips is at least one more than the number of the one or more memory chips. Each of the error correction code memory chips are arranged together with the memory chips of one of the ranks.
REFERENCES:
patent: 7320100 (2008-01-01), Dixon et al.
patent: 2005/0047250 (2005-03-01), Ruckerbauer et al.
patent: 2006/0171247 (2006-08-01), Hoppe et al.
patent: 2006/0187756 (2006-08-01), Ho et al.
patent: 2007/0058408 (2007-03-01), Ruckerbauer et al.
Edell Shapiro & Finnan LLC
Lamarre Guy J
Qimonda AG
LandOfFree
Memory module with ranks of memory chips does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Memory module with ranks of memory chips, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory module with ranks of memory chips will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2637614