Static information storage and retrieval – Read/write circuit – Bad bit
Patent
1983-06-02
1986-01-14
Hecker, Stuart N.
Static information storage and retrieval
Read/write circuit
Bad bit
365 51, G11C 2900, G11C 502
Patent
active
045649243
ABSTRACT:
An integrated memory module, includes at least one normally addressable cell array with edges and a matrix of memory cells disposed in rows and/or columns, the rows and/or columns being mutually spaced apart by a given distance, and redundant or spare memory cells disposed in rows and/or columns at the edges of the cell array for connection instead of defective rows and/or columns of memory cells in the cell array, the rows and/or columns of redundant memory cells being spaced apart from each other and from the rows and/or columns of memory cells of the cell array by distances being greater than the given distance.
REFERENCES:
patent: 4471472 (1984-09-01), Young
Gossage Glenn A.
Greenberg Laurence A.
Hecker Stuart N.
Lerner Herbert L.
Siemens Aktiengesellschaft
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