Memory module with equal driver loading

Details Memory module with equal driver loading Memory module with equal driver loading

2001-06-15

2004-03-30

Dinh, Son T. (Department: 2824)

Static information storage and retrieval

Interconnection arrangements

C365S051000, C365S230030

Reexamination Certificate

active

06714433

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
Not applicable.
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
Not applicable.
REFERENCE TO A MICROFICHE APPENDIX
Not applicable.
BACKGROUND OF THE INVENTION
This invention relates to memory expansion modules for expanding memory in computer systems and more particularly to modules having reduced and substantially equal loads on signal drivers and minimized access times.
Many modern computer systems allow for memory expansion by way of single inline memory modules (SIMMs) and/or dual inline memory modules (DIMMs). Typically, SIMMs and DIMMs include small, compact circuit boards that are designed to mount easily into an expansion socket mounted on another circuit board, such as a computer motherboard. To mount in the expansion socket, SIMMs and DIMMs typically include an edge connector comprising a plurality of contact pads, with contact pads typically being present on both sides of the circuit board. On SIMMs, opposing contact pads are connected together (i.e. shorted), and thus carry the same signal, while at least some of the opposing contact pads on DIMMs are not connected, thus allowing different signals to be carried. Due to this, higher signal density may be accommodated by DIMMs.
Memory elements mounted on SIMMs and DIMMs are typically Dynamic Random Access Memory (DRAM) chips or Synchronous Dynamic Random Access Memory (SDRAM) chips. In either case, the chips must be supplied with various address, control, and data signals for reading data from, or writing data to, the memory chips. It should be recognized that each input to a memory chip represents a load, mostly capacitive, on the signal driver driving it. In addition, printed circuit board conductors (often called traces) which connect a signal driver to the chip inputs also represent loads which may include inductance as well as capacitance and resistance. The total load on a signal driver includes the sum of the chip inputs connected to the line and loading associated with the conductors which carry the signals to the various chip inputs. When the output at a signal driver changes state, e.g. from logical zero to logical one, it takes some time for the signal levels at the chip inputs to reach and stabilize at the desired voltage. This “settling” or stabilization time is related to the characteristics of the circuit including the power driving the signal line and the loading on the line. This settling time must be included in calculating the minimum time required to access a memory device. Accordingly, this settling time can limit the maximum speed at which the system incorporating the memory may operate.
SIMMs and DIMMs can have various total memory capacities; for example,
64
,
128
or
256
megabyte capacities. The various capacities may be selected in several ways. The first is selection of memory chips having a given address space and byte size. For example, a chip may have a four-megabyte address space, i.e. four million separate addressable memory locations, with each byte being sixteen bits. Such a chip can provide storage of four million sixteen-bit words. Second, for a given size of memory chip, module capacity can be increased by using multiple chips on a board and increasing data bus width so that the data at an addressed location in each chip can be read out to the bus simultaneously. For example, if three four megabyte chips with sixteen bit bytes are used, the bus width would need to be at least forty-eight to allow the bytes at a selected address on each chip to be read out to the bus at the same time. A module with three four megabyte chips with sixteen bit bytes can be considered to have a total capacity of twelve million sixteen bit bytes, but may be called a twenty-four megabyte memory because an eight bit byte is often considered to be the standard byte size. A memory subsystem or decoder may then select which of the bytes is the one, or two in case the system is using sixteen-bit words, which has been requested based on its position on the bus. Third, if it is desired to add more chips without increasing the data bus width, the memory chips may be arranged in banks with their data outputs coupled to one set of data bus lines. For example, two banks each having three of the above-described chips can be placed on one board, with each bank having its data outputs coupled to the same forty-eight data bus conductors. An additional address line, or bank select line, may then be used to select only one bank to be actively connected to the data bus at any given time. Such a two-bank module would have twice the total capacity of a module with only one bank.
The fact that memory modules may be implemented with various numbers of chips can cause a problem in overall computer system operation. Typically, a module having more memory chips represents a larger load on the address and control signal lines. This increased load increases the time for signals to stabilize at the memory chip inputs, thereby increasing the required memory access time and generally slowing system operation. The memory system clock must be selected to accommodate the memory access time for all memory modules. Accordingly, the clock must be selected to operate properly with the modules having the longest access time. It would be desirable to minimize the access time for memory modules to allow increased clock speed and thus enhanced system performance. In addition, it would be desirable to have modules with substantially the same access time regardless of their capacity or number of memory chips so the modules could be easily interchanged in the system.
While the ability to expand memory module capacity by adding memory chips is an advantage in designing systems, it creates a problem because access time increases as the number of chips increases and adds more loading to the signal drivers. Thus, the flexibility of design has a negative impact on system performance by requiring the clock to be slow enough to work with a module with a maximum number of memory chips. In similar fashion, use of modules with more than one bank of memory chips provides design flexibility, for example, by allowing use of modules with one or two banks populated with memory chips. But, it again creates the problem that a two-bank module typically has twice the loading on the signal drivers as a one-bank module which causes a longer memory access time and therefore the system clock must be slowed to accommodate the slowest modules, i.e. those with both banks filled.
SUMMARY OF THE INVENTION
A memory module is disclosed which has at least two memory chips and includes a signal buffer with at least two sets of outputs which replicate control and address signals and drive these signals to the memory chip inputs. The signal buffer outputs are coupled to subsets of the total number of memory chips so that loading on each output is less than the total loading of all chip inputs, resulting in reduced access time. The buffer and memory chips are positioned, and signals are routed, to reduce and equalize the loading on each driver and thereby reduce memory access time.
In another embodiment, a memory module has locations for mounting multiple banks of memory chips (two banks in the specific embodiment of the invention described herein), but is designed to be fully functional with a single bank of memory chips. Each module includes signal drivers having a plurality of sets of outputs replicating a set of input signals, with each output set coupled to a separate bank. Memory access time is the same whether one bank or multiple banks are populated with memory chips.
A computer memory may be expanded by using only modules which have substantially equal access time regardless of capacity of the module.


REFERENCES:
patent: 5260892 (1993-11-01), Testa
patent: 5319591 (1994-06-01), Takeda et al.
patent: 5790447 (1998-08-01), Laudon et al.
patent: 5831890 (1998-11-01), Selna et al.
patent: 5973951 (1999-10-01), Bechtolsheim et al.
patent: 6038132 (2000-03-01), Tokunaga et al.
patent: 6370053 (2002-04-01), Chang et a

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