Memory module using dram and method of refreshing the memory mod

Details Memory module using dram and method of refreshing the memory mod Memory module using dram and method of refreshing the memory mod

1994-05-27

1995-12-12

Nguyen, Viet Q.

Static information storage and retrieval

Read/write circuit

Data refresh

365228, 395433, 395442, G06F 1110

Patent

active

054756456

ABSTRACT:
The present invention provides a memory module using a large capacity DRAM without a self-refresh mode, which maintains the contents of the memory irrespective of non-input of a refresh signal from a computer. A memory module (20) includes twenty DRAMs (24) soldered on a surface and rear face of a substrate (22). A connector (26) equiped on an edge of the substrate (22) is inserted into a memory extension slot (8) of a computer (1) to connect the substrate (22) electrically with the computer (1). When the computer (1) outputs refresh signals RASm and CASn within or at intervals of 500 nanoseconds, a gate array (28) included in the memory module (20) outputs these RASm and CASn signals to the DRAMs (24). When 500 nanoseconds have elapsed since fall of both the RASm and CASn signals to a low level, on the other hand, the gate array (28) generates artificial refresh signals RFRS and RFCS, splits the RFRS signal into five and the RFCS signal into four, and outputs the split signals to the DRAMs (24).

REFERENCES:
patent: 4977537 (1990-12-01), Dias et al.
patent: 5229970 (1993-07-01), Lee et al.
patent: 5247655 (1993-09-01), Khan et al.
patent: 5262998 (1993-11-01), Mnich et al.
patent: 5365487 (1994-11-01), Patel et al.

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