Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
1999-08-23
2002-08-27
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C714S742000, C365S201000
Reexamination Certificate
active
06442718
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to Automated Test Equipment (ATE) for memory modules, and more specifically, to methods of making the test environment more closely match the application environment of the tested memory module.
2. Description of the Relevant Art
Automated test equipment (ATE) is widely used in the electronics industry to insure that electronic devices meet specifications and functionality requirements. Automated test equipment exists for nearly every type of testable electronic device. Typically, test equipment is configured to test a certain type of electronic device. For example, some testers are dedicated to testing circuit boards, while others test individual chips, and others may test memory modules.
Most automated test equipment can perform a wide variety of tests on a given electronic device. The three main types of tests are parametric testing, functional testing, and testing for manufacturing defects. Parametric testing checks a device for electrical characteristics and parameters, such as voltages, currents, resistances, capacitance, and so forth. Functional testing checks a device for proper functionality. Typically, a group of test signals, known as test vectors, are applied to the device under test (DUT), and the tester then checks the responses to the applied test signals to ensure proper functionality. Testing can also be done exclusively to check for manufacturing defects. Typical manufacturing defects that are tested for include short circuits, open circuits, misoriented parts and wrong parts. Testing for manufacturing defects often overlaps with parametric testing and functional testing.
A typical test system contains two basic elements. The first of these elements is a testing unit, sometimes referred to as an instrument bay. A typical testing unit includes voltage and current sources, signal generators, a variety of measurement equipment, and a number of relays for connecting various sources and instruments to the device under test. The second element is an adapter unit which couples the device under test to the testing unit. The form of the adapter unit will vary with the type of device to be tested. For example, an adapter for testing a circuit board with test points will typically be a bed-of-nails fixture, while a memory module tester will use a specialized circuit board, known as a loadboard, to couple the device under test to the testing unit.
As previously stated, automated test equipment exists for a wide variety of electronic devices, including testers which are specific to memory modules. Testers specific to memory modules typically perform a number of parametric and functional tests on various types of memory modules. Parametric tests include tests for timing, current output on given pins, and current leakage tests between given pins. Functional tests include read/write tests to given blocks of memory cells and tests of certain signal lines, such as chip enable lines and write enable lines.
A typical memory module test system couples the device under test to the testing unit through a loadboard. A loadboard is a specially designed circuit board having a variety of electrical loads analogous to the application environment. The loadboard also includes a number of signal lines, which serve as transmission lines for test system drivers. These test system drivers are used to drive test signals to the device under test.
One factor limiting the accuracy of automated test systems is the difference between the testing environment and the application environment. Since these environments have different electrical characteristics, accuracy for some types of tests performed can be compromised. This is particularly true in test systems for memory modules. As computers have become faster, the requirement for memory modules operating at higher speeds has increased correspondingly. Differences in resistive and capacitive loads in the test system with respect to the application environment can alter the timing of various signals. For example, the differences between the electrical environments of the application and the tester may result in a lower maximum slew rate (i.e. the rate of change of a signal) when a memory module is under test. This can place an upper limit on the frequency at which the memory module can be tested, and often times this frequency is less than that of the application environment.
For a memory module test system, the difference between the electrical environments of the application and the test system can be reduced through the careful design of the loadboard. However, this can only overcome some of the limitations imposed by the test system with respect to the application environment. One such limitation results from the output impedance of the test system drivers. In many cases, driver output impedance is greater than the typical line impedances in the application environment. For example, a memory module test system may include drives that have an output impedance of 50 ohms, while the typical line impedance in the application environment is 25 ohms. This impedance mismatch can result in a slower slew rate for the device under test. As a result of the slower slew rate, tests may be limited in frequency, and often times this frequency will be less than the operating frequency of the application environment. The impedance mismatch may also skew various test and timing signals, further limiting the frequency of the test. With these considerations in mind, it would be desirable to more closely match the electrical environments of the tester and application in by matching driver impedance to the line impedance of the application.
SUMMARY OF THE INVENTION
The problems outlined above may in large part be solved by a memory module test system with reduced driver output impedance in accordance with the present invention. In one embodiment, a memory module tester includes a testing unit and a loadboard. The testing unit contains a plurality of driver circuits for driving test signals to the memory module under test. The testing unit also contains various instruments for receiving output signals from the device under test. The testing unit generates all test signals and test vectors required to perform a test on the memory module, and is configured to determine whether the device under test meets the required specifications, by comparing received output signals with known acceptable values.
The loadboard is used to couple the memory module to the test system. The loadboard includes a plurality of resistors and capacitors, and is designed to electrically approximate the application environment of the memory module to be tested. The loadboard includes a socket in which the memory module to be tested can be inserted. Circuit lines on the loadboard serve as transmission lines, and are electrically coupled to the driver circuits of the testing unit. The loadboard also includes a plurality of jumper wires. The wires are soldered to circuit pads or vias located on the boards. Each via is electrically connected to a circuit line associated with a driver circuit. The jumper wires are used to create short circuits between pairs of circuit lines.
As previously stated, the testing unit generates all test signals for test system. The test signals are driven to the device under test through the loadboard via driver circuits. The output impedance of each driver circuit is approximately 50 ohms in this embodiment. For each test signal generated, a duplicate test signal is driven to the loadboard through a second driver circuit. The circuit lines associated with the two duplicate test signals are shorted together by the jumper wire on the loadboard. Since the two driver circuits share a common ground, shorting them together effectively places them in parallel. By placing two driver circuits in parallel, the effective output impedance of the drivers is reduced by half, to approximately 25 ohms.
Thus, in various embodiments, the memory module test system with reduced line driver impedance may allow the te
Jeffrey David
Krow-Lucal Steven C.
Tran Dong
Conley Rose & Tayon PC
De'cady Albert
Kivlin B. Noäl
Sun Microsystems Inc.
Torres Joseph D.
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