Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination
Reexamination Certificate
2007-02-20
2007-02-20
Chang, Daniel D. (Department: 2819)
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Bus or line termination
C365S230030
Reexamination Certificate
active
10997406
ABSTRACT:
For ODT (on-die termination) control within a memory module system, just one pin from the memory controller is used for sending command signals indicating an activated one of the memory devices. The activated memory device includes components that are turned on for generating the ODT control signal for controlling an ODT circuit of inactivated memory device(s). The components for generating an ODT control signal within the inactivated memory devices are turned off for minimized power consumption.
REFERENCES:
patent: 6307791 (2001-10-01), Otsuka et al.
patent: 6538951 (2003-03-01), Janzen et al.
Korean Patent Application No. 1020020048708 to Kyung, having Publication date of Apr. 26, 2003 (w/ English Abstract page).
Japanese Patent No. JP2003068082 to Yoshinori, having Publication date of Feb. 27, 2003 (w/ English Abstract page).
Cho Jeong-Hyeon
Lee Jae-Jun
So Byung-Se
Chang Daniel D.
Choi Monica H.
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