Static information storage and retrieval – Read/write circuit
Reexamination Certificate
2003-10-24
2004-11-16
Le, Vu A. (Department: 2824)
Static information storage and retrieval
Read/write circuit
C365S226000, C365S189040
Reexamination Certificate
active
06819598
ABSTRACT:
BACKGROUND OF INVENTION
The invention relates to a memory module for use as main memory or VRAM (Video Random Access Memory), information processing apparatus, method for initialization relating a memory module, and a program.
In general, features of high-speed memories for use in personal computers such as DDR-SDRAM (Double Data Rate Static Dynamic Random Access Memory) slightly vary depending on their suppliers and types. Thus, when such high-speed memory is driven, the output strength of the access signal by a driver needs to be adjusted so as to adapt it to its supplier and type.The adjustment is performed by a configuration program (basic input/output system or BIOS) by providing optimal access parameters and the like to the memory controller. In such a case, the configuration program needs to know in advance what type of memory module is present.
As such, recent DIMM (Dual Inline Memory Module) type-memory module is provided with ROM (Read-Only Memory) on which its specification is recorded so that a configuration program can provide optimal parameters to the memory controller based on information recorded on the ROM. Such a ROM records many pieces of information including a supplier, memory capacity, and access speed, etc. The function for informing the BIOS of the specification of DIMM with ROM on DIMM in that way is known as a SPD (Serial Presence Detect) function.
Meanwhile, a technology is also known where only an identification (ID) number is given to the IMM and information relating to the configuration of the DIMM is recorded as a table on ROM provided in the system unit of a personal computer (see, for example, U.S. Pat. No. 5,727,182 and JP8305629A2). In this case, in setting various parameters relating to the DIMM, corresponding configuration parameters can be obtained from the table based on the ID number read from the DIMM.
On the other hand, for reasons of cost or supply, memory from several limited suppliers may be implemented as high-speed memory such as VRAM (Video RAM) deployed on a main board. Although it is necessary to identify the type of VRAM in initialization also in this case, providing ROM for identifying VRAM is not feasible in terms of cost since VRAM is not as generic as DIMM. As such, bits for identification are currently provided on the main board.
In this case, the procedure of initialization relating to VRAM is as follows; first, the type of VRAM is identified by reading the identification bits; then parameters corresponding to the type are obtained from the table and set to the memory controller; and arbitrary data is then written to a predetermined address, and check is made if the written data can be read to determine the capacity of the VRAM.
The above-mentioned SPD function, however, is disadvantageous in terms of cost and space because ROM has to be provided on the memory module.
The technology for providing an ID number on DIMM above requires addition of wires and hardware on the main board since the ID number should be read via a gate circuit, an ISA (Industry Standard Architecture) bus, and a processor bus.
Also, since the aforementioned technology for VRAM provides bits for identifying the VRAM on the main board, a main board with a different type of VRAM implemented thereon has also different implementation parts other than memory, thus needs to be handled as a different part in management. The technology is therefore disadvantageous in terms of management efficiency.
In view of such disadvantages in conventional art, an object of the invention is to allow a memory module to be easily identified without requiring wires or parts to be added in a computer system unit, i.e., a main board, or ROM to be provided on the memory module.
SUMMARY OF INVENTION
To attain the object, the memory module according to the invention comprises a memory array for storing data, an ID information output circuit for outputting ID information for identifying memory modules, and output switching means for selectively switching output from the memory array and output from the ID information output circuit to be output, wherein the output switching means selects output from the ID information output circuit instead of output from the memory array until the memory module is initially written after power supply to the memory module has been started.
The memory module may be VRAM and main memory, for example. Modules for expansion may be also possible. The ID information may include 4-bit information that identifies the supplier of the memory module or 8-bit information that identifies the supplier and type of the memory module. The ID information output circuit may be one that has output terminals corresponding to each bit and a circuit that grounds respective terminals or connects them to a predetermined voltage source so that voltages corresponding to on and off of the bits are applied to each output terminal. The output switching means may be a selector that switches between output from the ID information output circuit and output from the memory array to be output in accordance with on and off of a predetermined input control signal, for example.
With this configuration, when power supply to the memory module is started and initialization of the memory module begins, the output switching means selects output from the ID information output circuit before the memory module is initially written. Therefore, if reading is performed at any address before the initial writing is done, ID information for the memory module will be read out from the ID information output circuit. The read out ID information is used to obtain corresponding information for initialization from a table. Subsequently, after writing is done once, the output switching means will select output from the memory array, so data from the memory array will be read out at subsequent reading.
Thus, in initialization of the memory module, ID information can be obtained simply by performing readout before the memory module is initially written. If the memory module is of a conventional type, data within the memory array would be read out when reading is done before initial writing. In that case, the memory array has nothing written to it, thus an undefined value, e.g. hexadecimal FF would be read out. Thus, even when a conventional memory module and the memory module of the invention are implemented concurrently, it is possible to easily distinguish the memory module of the invention from the conventional one and perform initialization for the memory module of the invention based on obtained ID information, and in a conventional way for the conventional one. The application of the invention does not require addition of parts and circuits to the computer system unit or provision of ROM on the memory module. Slight modification to an initialization program and addition of a simple circuit onto the memory module will suffice.
The memory module may further comprise a switch control means for controlling the output switching means such that it selects output from the ID information output circuit from the initiation of power supply to initial writing, and subsequently selects output from the memory array, based on reset detection signal that is generated when the power supply is started and a signal corresponding to a signal indicating writing to the memory module.
In that case, the memory module may further comprise a reset detection means for outputting the reset detection signal in response to the initiation of power supply to the memory module.
In a more specific aspect of the invention, the memory module comprises a memory array, an ID information output circuit for outputting identification information for identifying memory modules, a flip-flop that is set and reset in accordance with a reset detection signal that is generated when power supply to the memory module is started and a signal corresponding to a signal indicating writing to the memory module, and a selector for selectively switching between output from the memory array and output from the ID information output circuit to be output d
Fujita Norio
Kubota Tetsu
Yamazaki Satoshi
C. Li Todd M.
International Business Machines - Corporation
Le Vu A.
Nguyen Dang
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