Memory module package with address bus buffering

Details Memory module package with address bus buffering Memory module package with address bus buffering

1996-04-10

1997-10-21

Dinh, Son T.

Static information storage and retrieval

Hardware for storage elements

365 51, 365 63, 36523003, G11C 506

Patent

active

056803427

ABSTRACT:
Systems and methods for connecting multiple memory modules to a computer system while controlling address bus and data bus loading and termination effects. In one form, the modules are connected to a printed circuit board carrying the address and data buses using dendrite enhanced bonds between module contacts and printed circuit board pads. The address bus loading which typically characterizes the addition of memory to a computer system is minimized through the inclusion of an address buffer module with each group of memory modules in a module expansion carrier. Data bus termination characteristics are controlled using jumpers within the modules. The invention is particularly suited for use with modules configured with chip edge interconnect technology, allowing the computer system user to expand the system memory without unduly effecting the address bus and data bus line characteristics.

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