Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
2002-05-31
2003-10-21
Nguyen, Tan T. (Department: 2818)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S225700
Reexamination Certificate
active
06636447
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to a memory module having memory cells and a predetermined number of redundant memory cells which are used for repairing defective memory cells. A first address circuit is provided, which activates a predeterminable number of memory cells via address lines in dependence on a predetermined address. A second address circuit is provided, which is connected to the redundant memory cells via second address lines. The second address circuit, in the event that a defect address of at least one defective memory cell is supplied, activates the redundant memory cells assigned to the defect address. A selection circuit is provided, which is connected to the first address circuit. The selection circuit defines the predeterminable number of memory cells which are activated by the first address circuit in the event of an address being supplied.
The invention also pertains to a method for activating memory cells, in particular for writing and/or reading data to and/or from memory cells of a memory module. A defined number of memory cells are activated via an address, redundant memory cells are provided for defective memory cells and are activated after a repair instead of the defective memory cells with the address of the defective memory cells. The number of memory cells which can be activated under an address is defined by a check of a number datum.
Furthermore, the invention pertains to a method for repairing defective memory cells of a memory module by way of redundant memory cells. A predeterminable number of memory cells are able to be activated via an address, in particular data being written to the memory cells or read therefrom. The predeterminable number is predetermined in a manner dependent on a number datum, the memory cells are checked for correct functioning, and memory cells that have been identified as defective are replaced by redundant memory cells, and the redundant memory cells are activated when an address of defective memory cells is present.
Memory cells are used in various types of memory modules, such as, for instance, in a DRAM memory. DRAM memories have a multiplicity of memory cells which are fabricated by means of a multiplicity of complex semiconductor processes. Despite very great efforts, it is not possible to fabricate all the memory cells of a memory module without any defects. To ensure, however, that the entire memory module is not defective on account of individual defective memory cells, additional, so-called redundant memory cells are arranged on the memory module, which are used during a repair of defective memory cells. By way of example, if it is ascertained at the end of the fabrication process, when checking the memory cells, that a memory cell is defective, then the address of the defective memory cell is diverted to a redundant memory cell in an address decoder. During later use of the memory module, it is not apparent that, instead of the defective memory cell, the redundant memory cell is actually being driven in the event of the addressing of the defective memory cell.
It has been found that repairing individual memory cells is not economic. Therefore, memory cells of an entire word line or memory cells of an entire bit line are replaced by correspondingly redundant memory cells of an entire word line or of an entire bit line. So-called laser fuses, which represent fuses, are used for programming the new address. By blowing the fuse, a defined electrical state is set at the input of the fuse. The address of a defective memory cell is defined, for example, by the arrangement of a plurality of electrical fuses and the programming thereof. If the defective memory cell is then connected to an address decoder, the address decoder recognizes from the comparison with the fuses that this address is an address of a defective memory cell. The defective address is thereupon replaced by a stored replacement address of a redundant memory cell and the redundant memory cell is activated instead of the defective memory cell.
Furthermore, it is known to provide electrical fuses via which additional SRAM memory cells are used as redundant memory cells. The SRAM memory cells can be activated via the electrical fuses even in the already constructed memory module.
Memory modules have memory arrays which can be switched into different address configurations via corresponding programming. By way of example, 4, 8 or 16 memory cells can be assigned to a single address by a corresponding selection. Consequently, the number of memory cells that are driven when an individual address is prescribed depends on the type of programming of the memory module. To date, when repairing a memory cell of an address, the maximum possible number of redundant memory cells has always been addressed under the address of the defective memory cell.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a memory module, a method for activating memory cells, and a method for repairing defective memory cells, which overcomes the above-mentioned disadvantages of the heretofore-known devices and methods of this general type and wherein, with the number of redundant memory cells remaining the same, a larger number of defective memory cells can be repaired.
With the foregoing and other objects in view there is provided, in accordance with the invention, a memory module, comprising:
a plurality of memory cells and a predetermined number of redundant memory cells for repairing defective memory cells;
a first address circuit configured for activating a predeterminable number of memory cells via address lines in dependence on a predetermined address;
a second address circuit connected to the redundant memory cells via second address lines;
the second address circuit, upon receiving a defect address of at least one defective memory cell, activating redundant memory cells assigned to the defect address; and
a selection circuit connected to the first address circuit and to the second address circuit, the selection circuit defining the predeterminable number of memory cells to be activated by the first address circuit in event of an address being supplied, and the selection circuit prescribing for the second address circuit how many redundant memory cells are to be activated under a defect address.
With the above and other objects in view there is also provided, in accordance with the invention, a method of activating memory cells, in particular for writing data to and for reading data from a memory module. The method comprises:
activating a defined number of memory cells via an address;
providing redundant memory cells for defective memory cells and, after a repair, activating the redundant memory cells instead of the defective memory cells with the address of the defective memory cells;
checking a number datum to thereby define the number of memory cells that can be activated under an address, and wherein, when redundant memory cells are activated, checking the number datum and activating a predeterminable number of redundant memory cells in dependence on the number datum.
With the above and other objects in view there is further provided, in accordance with the invention, a method for repairing defective memory cells of a memory module, which comprises:
providing a memory module with memory cells and redundant memory cells, wherein a predeterminable number of memory cells are activatable via an address, and the predeterminable number is predetermined in dependence on a number datum;
checking the memory cells for correct functioning;
identifying defective memory cells and replacing the defective memory cells by redundant memory cells, the redundant memory cells being activated when an address of defective memory cells is present; and
defining a number of redundant memory cells that are addressed for an address instead of the defective memory cells in accordance with the number datum.
One advantage of the invention is that, during a repair of defective memory cells, account is taken of the data depth to w
Greenberg Laurence A.
Infineon - Technologies AG
Locher Ralph E.
Nguyen Tan T.
Stemer Werner H.
LandOfFree
Memory module, method for activating a memory cell, and... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Memory module, method for activating a memory cell, and..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory module, method for activating a memory cell, and... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3174395