Electrical computers and digital data processing systems: input/ – Intrasystem connection – System configuring
Patent
1998-06-16
1999-07-27
Auve, Glenn A.
Electrical computers and digital data processing systems: input/
Intrasystem connection
System configuring
710 9, G06F 1300
Patent
active
059283432
ABSTRACT:
A method and apparatus for assigning identification values to memories. A master resets identifiers of a first memory and a second memory by sending a reset signal on a line that is coupled in a daisy-chained manner to the first and second memories and also coupled to the master. The master places a first identification value on a data bus coupled to the master and to the first and second memories. The first memory stores the first identification value on the data bus as an identifier for the first memory when the master sends a first storage signal to the first memory via the daisy-chained line. The master places a second identification value on the data bus. The second memory stores the second identification value on the data bus as an identifier for the second memory when the master sends a second storage signal to the second memory via the daisy-chained line.
REFERENCES:
patent: 3633166 (1972-01-01), Picard
patent: 3691534 (1972-09-01), Varadi et al.
patent: 3740723 (1973-06-01), Beausoleil et al.
patent: 3758761 (1973-09-01), Henrion
patent: 3771145 (1973-11-01), Wiener
patent: 3821715 (1974-06-01), Hoff, Jr. et al.
patent: 3882470 (1975-05-01), Hunter
patent: 3924241 (1975-12-01), Kronies
patent: 3969706 (1976-07-01), Proebsting et al.
patent: 3972028 (1976-07-01), Weber et al.
patent: 3975714 (1976-08-01), Weber et al.
patent: 3983537 (1976-09-01), Parsons et al.
patent: 4007452 (1977-02-01), Hoff, Jr.
patent: 4038648 (1977-07-01), Chesley
patent: 4099231 (1978-07-01), Kotok et al.
patent: 4191996 (1980-03-01), Chesley
patent: 4205373 (1980-05-01), Shah et al.
patent: 4234934 (1980-11-01), Thorsrud
patent: 4247817 (1981-01-01), Heller
patent: 4249247 (1981-02-01), Patel
patent: 4263650 (1981-04-01), Bennett et al.
patent: 4286321 (1981-08-01), Baker et al.
patent: 4306298 (1981-12-01), McElroy
patent: 4315308 (1982-02-01), Jackson
patent: 4333142 (1982-06-01), Chesley
patent: 4354258 (1982-10-01), Sato
patent: 4355376 (1982-10-01), Gould
patent: 4373183 (1983-02-01), Means et al.
patent: 4375665 (1983-03-01), Schmidt
patent: 4385350 (1983-05-01), Hansen et al.
patent: 4443864 (1984-04-01), McElroy
patent: 4449207 (1984-05-01), Kung et al.
patent: 4458357 (1984-07-01), Weymouth et al.
patent: 4468738 (1984-08-01), Hansen et al.
patent: 4470114 (1984-09-01), Gerhold
patent: 4480307 (1984-10-01), Budde et al.
patent: 4481625 (1984-11-01), Roberts et al.
patent: 4481647 (1984-11-01), Gombert et al.
patent: 4488218 (1984-12-01), Grimes
patent: 4493021 (1985-01-01), Agrawal et al.
patent: 4494186 (1985-01-01), Goss et al.
patent: 4500905 (1985-02-01), Shibata
patent: 4513370 (1985-04-01), Ziv et al.
patent: 4513374 (1985-04-01), Hooks, Jr.
patent: 4519034 (1985-05-01), Smith et al.
patent: 4566098 (1986-01-01), Gammage et al.
patent: 4570220 (1986-02-01), Tetrick et al.
patent: 4571672 (1986-02-01), Hatada et al.
patent: 4595923 (1986-06-01), McFarland
patent: 4608700 (1986-08-01), Kirtley, Jr. et al.
patent: 4630193 (1986-12-01), Kris
patent: 4635192 (1987-01-01), Ceccon et al.
patent: 4646270 (1987-02-01), Voss
patent: 4649511 (1987-03-01), Gdula
patent: 4649516 (1987-03-01), Chung et al.
patent: 4654655 (1987-03-01), Kowalski
patent: 4656605 (1987-04-01), Clayton
patent: 4660141 (1987-04-01), Ceccon et al.
patent: 4675813 (1987-06-01), Locke
patent: 4706166 (1987-11-01), Go
patent: 4719627 (1988-01-01), Peterson et al.
patent: 4745548 (1988-05-01), Blahut
patent: 4757473 (1988-07-01), Kurihara et al.
patent: 4761799 (1988-08-01), Arragon
patent: 4764846 (1988-08-01), Go
patent: 4766536 (1988-08-01), Wilson, Jr. et al.
patent: 4770640 (1988-09-01), Walter
patent: 4775931 (1988-10-01), Dickie et al.
patent: 4779089 (1988-10-01), Theus
patent: 4785394 (1988-11-01), Fischer
patent: 4785396 (1988-11-01), Murphy et al.
patent: 4803621 (1989-02-01), Kelly
patent: 4811202 (1989-03-01), Schabowski
patent: 4818985 (1989-04-01), Ikeda
patent: 4831338 (1989-05-01), Yamaguchi
patent: 4837682 (1989-06-01), Culler
patent: 4858112 (1989-08-01), Puerzer et al.
patent: 4860198 (1989-08-01), Takenaka
patent: 4862158 (1989-08-01), Keller et al.
patent: 4882669 (1989-11-01), Miura et al.
patent: 4920486 (1990-04-01), Nielson
patent: 4933835 (1990-06-01), Sachs et al.
patent: 4937733 (1990-06-01), Gillett, Jr. et al.
patent: 4939510 (1990-07-01), Masheff et al.
patent: 4940909 (1990-07-01), Mulder et al.
patent: 4945471 (1990-07-01), Neches
patent: 4947484 (1990-08-01), Twitty et al.
patent: 4954992 (1990-09-01), Kumanoya et al.
patent: 4964038 (1990-10-01), Louis ee al.
patent: 4965792 (1990-10-01), Yano
patent: 4975763 (1990-12-01), Baudouin et al.
patent: 4982400 (1991-01-01), Ebersole
patent: 4998069 (1991-03-01), Nguyen et al.
patent: 4998262 (1991-03-01), Wiggers
patent: 5012408 (1991-04-01), Conroy
patent: 5021772 (1991-06-01), King et al.
patent: 5023488 (1991-06-01), Gunning
patent: 5038317 (1991-08-01), Callan et al.
patent: 5038320 (1991-08-01), Heath et al.
patent: 5051889 (1991-09-01), Fung et al.
patent: 5056060 (1991-10-01), Fitch et al.
patent: 5063561 (1991-11-01), Kimmo
patent: 5077693 (1991-12-01), Hardee et al.
patent: 5083260 (1992-01-01), Tsuchiya
patent: 5083296 (1992-01-01), Hara et al.
patent: 5093807 (1992-03-01), Hashimoto et al.
patent: 5107491 (1992-04-01), Chew
patent: 5111423 (1992-05-01), Kopec, Jr. et al.
patent: 5111464 (1992-05-01), Farmwald et al.
patent: 5117494 (1992-05-01), Costes et al.
patent: 5121382 (1992-06-01), Yang et al.
patent: 5129069 (1992-07-01), Helm et al.
patent: 5175831 (1992-12-01), Kumar
patent: 5179670 (1993-01-01), Farmwald et al.
patent: 5193149 (1993-03-01), Awiszio et al.
patent: 5193199 (1993-03-01), Dalrymple et al.
patent: 5220673 (1993-06-01), Dalrymple et al.
patent: 5226009 (1993-07-01), Arimoto
patent: 5247518 (1993-09-01), Takiyasu et al.
patent: 5317723 (1994-05-01), Heap et al.
patent: 5361277 (1994-11-01), Grover
patent: 5371892 (1994-12-01), Petersen et al.
patent: 5390149 (1995-02-01), Vogley et al.
patent: 5452420 (1995-09-01), Engdahl et al.
H. Schumacher, "CMOS Subnanosecond True-ECL Output Buffer", IEEE Journal of Solid-State Circuits, vol. 25, No. 1, pp. 150-154 (Feb. 1990).
International Search Report Dated Jul. 8, 1991 for PCT Patent Application No. PCT/US91/02590 filed Apr. 16, 1991.
T. Yang, M. Horowitz, B. Wooley, "A 4-ns 4K .times. 1-bit Two-Port BiCMOS SRAM", IEEE Journal of Solid-State Circuits, vol. 23, No. 5, pp. 1030-1040 (Oct. 1988).
J. Frisone, "A Classification for Serial Loop Data Communications Systems", Raleigh Patent Operations (Nov. 2, 1972).
A. Khan, "What's The Best Way to Minimize Memory Traffic", High Performance Systems, pp. 59-67 (Sep. 1989).
N. Margulis, "Single Chip RISC CPU Eases Systems Design", High Performance Systems, pp. 34-36, 40-41, 44 (Sep. 1989).
R. Matick, "Comparison of Memory Chip Organizations vs. Reliability in Virtual Memories", FTCS 12th Annual International Symposium Fault-Tolerant Computing, IEEE Computer Society Fault-Tolerant Technical Committee, pp. 223-227 (Jun. 22, 1984).
A. Agarwal et al., "An Evaluation of Directory Schemes for Cache Coherence," 15th Intern Symp. Comp. Architecture, pp. 280-289 (Jun. 1988).
A. Agarwal et al., "An Analytical Cache Model," ACM Trans. on Comp Sys., vol. 7, No. (2), pp. 184-215 (May 1989).
Beresford, "How to Tame High Speed Design," High-Performance Systems, pp. 78-83 (Sep. 1989).
J. Carson, "Advanced On-Focal Plane Signal Processing for Non-Planar Infrared Mosaics", SPIE, vol. 311, pp. 53-58 (1981).
G. Chesley, "Virtual Memory Integration," Submitted to IEETC (Sep. 1983).
E. Davidson, "Electrical Design of a High Speed Computer Package," IBM J. Res. Develop., vol. 26, No. 3, pp. 349-361 (May 1982).
F. Hart, "Multiple Chips Speed CPU Subsystems," High-Performance Systems, pp. 46-55 (Sep. 1989).
M. Horowitz et al., "MIPS-X: A 20-MIPS Peak 32-bit Micoprocessor with On-Chip Cache," IEEE J. Solid State Circuits, vol. SC-22, No. 5, pp. 790-798 (Oct. 1987).
S. Kwon et al., "Memory Chip Organizations for Improved Reliabilty in Virtual Memories," IBM Technical Disclosure Bulletin, vol. 25, No. 6, pp. 2952-2957 (Nov. 1982).
R. Pease et al., "
Farmwald Michael
Horowitz Mark
Auve Glenn A.
Rambus Inc.
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