Memory module having a two-transistor memory cell

Details Memory module having a two-transistor memory cell Memory module having a two-transistor memory cell

2001-08-30

2002-10-15

Zarabian, A. (Department: 2824)

Static information storage and retrieval

Systems using particular element

Capacitors

C365S187000

Reexamination Certificate

active

06466474

ABSTRACT:

BACKGROUND OF INVENTION
1. Field of the Invention
The present invention relates to a memory module, and more particularly, to a memory module with a simple structure that uses capacitors for storing data without refreshing.
2. Description of the Prior Art
With a development of an information industry, computer systems used for handling a great quantity of data are very popular in a broad spectrum of fields. An ability to deal with digital data makes the computer systems powerful. Not only personal digital assistants (PDA), portable computers, and personal computers for personal uses, but central control systems and switches for controlling the data of multiple users, all make use of the powerful computer systems. Aside from a central processing unit (CPU), a memory module, which helps the CPU operate more quickly, is a key factor for improving an efficiency of the computer system. When the computer system operates, the memory module stores the digital data and program codes, so that the CPU accesses the required data more quickly. Thus, the computer system operates more efficiently.
Please refer to
FIG. 1
, which is a circuit diagram of a memory module according to the prior art. The memory module
10
is a dynamic random access memory (DRAM) comprising a plurality of memory cells (in
FIG. 1
, only six memory cells A
1
-A
6
are shown). Corresponding to a placement of the memory cells are two parallel word lines PWL
1
and PWL
2
, running from top to bottom and used to connect with the memory cells. The word line PWL
1
is electrically connected to memory cells A
1
, A
3
, and A
5
. Similarly, the word line PWL
2
is electrically connected to memory cells A
2
, A
4
, and A
6
. Three parallel bit lines PBL
1
, PBL
2
and PBL
3
run from left to right, and are used to connect with the memory cells. The bit line PBL
1
is electronically connected to memory cells A
1
and A
2
. Similarly, the bit line PBL
2
is electronically connected to memory cells A
3
and A
4
. The bit line PBL
3
is electronically connected to memory cells A
5
and A
6
. The address circuit
12
controls each word line, and the bit access circuit
14
controls each bit line. The retrieve circuit
16
reads the data stored in the memory cells A
1
-A
6
.
In the memory module
10
, the structure of each memory cell is the same. The memory cell is capable of storing one bit of the digital data. Taking the memory cell A
1
for example, the memory cell A
1
according to the prior art comprises an access transistor Q
1
and a capacitor C
0
for storing charge. The access transistor Q
1
is a metal-oxide-semiconductor (MOS) transistor. A gate of the access transistor Q
1
is electrically connected to the word line at a node PN
1
, and a drain and a source of the access transistor Q
1
are electrically connected between the bit line and the capacitor C
0
.
Operation of the memory module
10
is illustrated as follows. When the memory module stores one bit of the digital data into the memory cell A
1
, the address circuit
12
increases the voltage of the word line PWL
1
, which is electrically connected to the memory cell A
1
, thereby turning on the access transistor. Simultaneously, the voltage of other word lines maintains a low level. Therefore, only the transistors of memory cells A
3
and A
5
, electronically connected to the same word line PWL
1
, are capable of conducting current. The bit access circuit
14
stores charge into the capacitor C
0
of the memory cell A
1
via the bit line PBL
1
. The quantity of charge stored on the capacitor C
0
determines the logic value represented by the memory cell. For example, if the memory module stores logic “
1
” into the memory cell, the bit access circuit
14
increases the voltage of the corresponding bit line, so that the charge can flow into the capacitor via the bit line and the conducting access transistor. On the contrary, if the memory module stores logic “
0
” into the memory cell, the bit access circuit
14
decreases the voltage of the corresponding bit line, so that the capacitor decreases its charge capacity by discharging via the conducting access transistor and the bit line. The small quantity of charge stored on the capacitor represents logic “
0
”.
When the memory module
10
reads one bit from a certain memory cell, the high voltage of the word line corresponding to the memory cell makes the access transistor conduct current. The retrieve circuit
16
detects the quantity of charge via the bit line and the conducting access transistor to retrieve the data. When the memory cell is storing the data, the access transistor turns off to break the connection between the capacitor and the word line until a next access begins.
As discussed above, the memory module
10
according to the prior art uses the charge stored in the capacitor to represent the logic value stored in the memory cell. Using the capacitor simplifies the circuit design of each memory cell, so as to decrease the area required for the circuit layout, and increases the density of the memory modules. However, when the memory module according to the prior art stores charge and the data, that is, when the capacitor is not electronically connected to the bit line, it is inevitable that charge leakage occurs. The charge leakage affects the quantity of charge stored in the capacitor and results in storing wrong data.
The prior art adopts a refresh operation for the memory module to recharge the capacitors. The access transistor of the memory cell conducts current during each refresh cycle, and the retrieve circuit
26
, or the bit access circuit
24
, supplies the capacitor with charge via the corresponding bit line. Nevertheless, the refresh operation makes control clocks and related circuitry very complicated. It is difficult to manufacture and use the memory module according to the prior art. Additionally, if the refresh cycle is too short, the repeated refresh operation interferes with normal access of the memory module. If the refresh cycle is too long, the charge leakage occurs continuously, so that the memory module is not capable of sustaining the correct data.
SUMMARY OF INVENTION
It is therefore a primary objective of the present invention to provide a memory module with two transistors to solve the above-mentioned problem.
Briefly, the claimed invention provides a memory module for storing digital data. The memory module comprises a plurality of memory cells, and a voltage source for biasing the memory cells. Each of the memory cells comprises an access transistor electronically connected to a word line and a bit line for receiving bits from the bit line when the word line turns on the access transistor. Each memory cell also comprises a switching circuit electronically connected to the access transistor, and a capacitor electronically connected to the switching circuit. The switching circuit turns on or off according to the bit data of the access transistor. The capacitor stores charge supplied by the switching circuit when the switching circuit turns on. On the contrary, the capacitor stores charge supplied by the voltage source when the switching circuit turns off. When the access transistor turns off, the switching circuit or the voltage source provides charge to the capacitor, so as to sustain the voltage level of the capacitor to compensate for charge leakage of the capacitor.
It is an advantage of the present invention that each memory cell can store data without refreshing a whole memory module.


REFERENCES:
patent: 5870329 (1999-02-01), Foss
patent: 6016268 (2000-01-01), Worley

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