Memory module for preventing skew between bus lines

Details Memory module for preventing skew between bus lines Memory module for preventing skew between bus lines

2001-06-21

2002-08-27

Mai, Son (Department: 2818)

Static information storage and retrieval

Interconnection arrangements

C365S052000

Reexamination Certificate

active

06442057

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a memory module, and more particularly, to a memory module for preventing skew between bus lines within the memory module.
2. Description of the Related Art
A memory module is provided with a plurality of memory chips and is electrically connected to external devices such as a memory controller and a microprocessor through module tabs which are inserted into and contact sockets. The memory chips are connected to each other through bus lines disposed on the memory module. The bus lines are connected to external bus lines through the module tabs and carry commands transmitted to the memory chips or data output from the memory chips.
FIG. 1
is a diagram illustrating a conventional memory module. The conventional memory module includes first through eighth memory chips M
1
, M
2
, . . . , M
8
. The memory chips M
1
through M
8
are connected to one another through a bus line
10
which is connected to an external bus line through a module tab
20
. The bus line has different line loads depending on physical distances to the memory chips M
1
through M
8
. For example, the waveforms of signals through a bus line
1
connected to the first memory chip Ml, through a bus line
5
connected to the fifth memory chip M
5
and through a bus line
8
connected to the eighth memory chip M
8
, respectively, are as shown in FIG.
2
.
In
FIG. 2
, the signal waveform on the bus line
5
connected to the fifth memory chip M
5
appears first because the fifth memory chip M
5
is nearest to the bus line
10
. Next, the signal waveform on the bus line
8
connected to the eighth memory chip M
8
appears with a little delay compared to the waveform on the bus line
5
. The signal waveform on the bus line
1
connected to the first bus line M
1
appears last. This is because the bus line
1
is longer than the bus line
5
and the bus line
8
. Therefore, a time delay occurs between the waveform on the bus line and the waveform on the bus line
1
. This time delay is referred to as skew and is represented by t
SKEW
.
When a signal transmitted through the bus line
10
is related to an operating command, such skew t
SKEW
causes the memory chips to operate at different times.
As a result, this skew hinders the high speed data processing between the memory module and an external memory controller or an external microprocessor.
Accordingly, a method for reducing skew between bus lines within a memory module is desired.
SUMMARY OF THE INVENTION
To solve the above problems, it is an object of the present invention to provide a memory module for reducing skew between bus lines.
Accordingly, to achieve the above object of the invention, in one embodiment, there is provided a memory module including a printed circuit board, a plurality of memory chips disposed on the printed circuit board, module tabs disposed at one edge of the printed circuit board, and bus lines connected to the module tabs, respectively, and connected to the memory chips. A portion of the bus line that is connected to the memory chips is formed as a closed circuit loop.
In one embodiment, each of the bus lines is connected to the memory chips through a circuitous or roundabout path which includes first and second paths of, in general, different lengths. The first and second paths of the roundabout path branch from each other at a position on the closed circuit loop.
In another embodiment, there is provided a memory module including a printed circuit board, a plurality of memory chips disposed on the printed circuit board, module tabs disposed at one edge of the printed circuit board, buffers connected to the module tabs, respectively, and bus lines connected to the outputs of the buffers, respectively, and connected to the memory chips. A portion of each of the bus lines that is connected to the memory chips is formed as a closed circuit loop. The buffers increase the transition speed of signals passing through the bus lines.
According to the present invention, each bus line on the memory module forms a closed loop, so that skew does not occur between control signals or output data, which are transmitted through the bus line.


REFERENCES:
patent: 4769558 (1988-09-01), Bach
patent: 5495435 (1996-02-01), Sugahara
patent: 6034878 (2000-03-01), Osaka et al.
patent: 5101205 (1993-04-01), None
patent: 7261895 (1995-10-01), None

Affiliated with

Also associated with

Rating

Memory module for preventing skew between bus lines does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Memory module for preventing skew between bus lines, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory module for preventing skew between bus lines will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2963711