Memory module controlling system

Details Memory module controlling system Memory module controlling system

1999-02-08

2001-06-26

Yoo, Do Hyun (Department: 2185)

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

C326S030000, C365S063000

Reexamination Certificate

active

06253284

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 87118598, filed Nov. 9, 1998, the full disclosure of which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a memory module controlling system. More particularly, the present invention relates to a system for controlling a high-speed memory module.
2. Description of Related Art
Memory is one of the most important components in a computer system. At present, dynamic random access memories (DRAMs) are one of the most commonly used memory chip. The development of DRAM is extremely fast these days. Memory capacity has increased from the former 1K bits per chip to more than 64M bits now. Although storage capacity has increased many folds, operating efficiency of DRAM has not improved that much. Compared with a processing device such as a microprocessor, the operating efficiency of DRAM is so poor that it can hardly match the speed of the microprocessor. Consequently, a number of complicated and expensive controlling systems are developed, mainly to increase the operating efficiency of memories. For example, synchronous random access memory caches (SRAM caches) and parallel arrays of DRAMs are recently developed memory controlling systems.
To resolve the problems of having a low operating efficiency and a complicated controlling scheme, Rambus corporation has developed a memory controlling system having a chip-to-chip bus interface, and has defined the protocols for its modular connection. This type of memory controlling system that follows a pre-defined set of rules for communication is generally referred to as having a direct Rambus channel configuration. Memories can be directly connected to a microprocessor, graphic processor or ASICs through a direct Rambus channel. The Rambus channel requires only a few high frequency carrier lines for carrying all the necessary information such as memory address, digital data and control signals. Memory module that uses the direct Rambus channel design approach and the protocols of communication are known as a Rambus DRAM module or a RIMM for short.
FIGS. 1A
,
1
B and
1
C are respectively a four-channel, a two-channel and a single channel direct Rambus channel type of memory and its control interfaces. Memory chips
10
are connected serially together through a direct Rambus channel
12
, and finally attached to a control interface
16
of a memory controller
14
. As shown in
FIGS. 1A through 1C
, all the memory chips
10
are divided between channel groups with the memory chips
10
in each group connected serially together via a single channel
12
. Since each channel
12
has a minimum data transmission rate of about 1.6G bits, the data transmission rates for the memory modules in
FIGS. 1A
,
1
B and
1
C are 6.4G bits, 3.2G bits and 1.6G bits, respectively. Hence, RIMM memory module is able to have a high operating efficiency but a low cost of production.
Although RIMM memory modules can operate at a very high speed, a high operating frequency of up to 400 MHz must be supplied. Hence, a terminal must be installed at the terminal of a channel for preventing reflection of high frequency signals.
FIG. 2A
is a sketch showing a RIMM having three RIMM memory modules
20
a
,
20
b
and
20
c
plugged into their respective memory slots. Through a single channel
24
, all the memory chips
22
a
,
22
b
and
22
c
in all three modules are connected serially together. The module
20
a
is connected to the control interface
26
a
of the memory controller
26
via the channel
24
. The last module
20
c
is connected to a terminal
28
and a clock pulse generator
29
via the same channel
24
. Therefore, the memory controller
26
, the memory modules
20
a
,
20
b
,
20
c
and the terminal
28
together form a complete signaling circuit. However, if only a single RIMM memory module is plugged into any one of the memory slots, a complete circuit between the memory controller
26
, the single memory module and the terminal
28
cannot be established. Under this circumstance, normal practice is to plug dummy RIMM modules such as
20
b′
and
20
c′
into the empty slots, as shown in FIG.
2
B. Each of these dummy RIMM modules do not have memory chips like a RIMM memory module, instead each dummy module only contains a circuit channel for passing signals. Hence, a complete circuit linking the memory controller
26
, the memory module
20
a
, the terminal
28
and the clock pulse generator
29
is now established, and information regarding memory address, data and control signals can be transmitted.
Therefore, the solution to signal cutoff when some slots contain no RIMM memory is to plug in dummy modules having a channel circuit therein as a substitute. By so doing, all the memory slots are occupied. The dummy modules must be unplugged whenever additional RIMM memory modules need to be installed. In addition, the fabrication of dummy modules adds to the cost of production.
In light of the foregoing, there is a need to provide an easier method of connecting RIMM memory modules that can save cost.
SUMMARY OF THE INVENTION
Accordingly, the purpose of the present invention is to provide a memory module controlling system that uses a simple method to form a complete signaling circuit linking memory modules, a terminal and a clock pulse generator.
In a second aspect, the invention provides a memory module controlling system that can detect state of occupation of the memory slots, and then forming channel connection between the last memory-occupied slot and a terminal device automatically.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a memory module controlling system. The memory module controlling system of this invention is capable of detecting the state of occupation of its memory slots such that a complete signaling channel between the memory modules and its terminal device can be established automatically. The memory module controlling system further comprises a multiplexer, an automatic detector and a terminal device. Each memory slot in the system transmits a signal to the automatic detector so that the state of occupation of each memory slot can be determined. Ultimately, a controlling signal reflecting the state of occupation of the slots is sent to the multiplexer.
Channel signals from each memory slot are transmitted to various input terminals of the multiplexer; meanwhile the output terminal of the multiplexer is connected to the terminal device. By sensing the controlling signal emitted from the automatic detector, the multiplexer is able to select one of its input terminals and connect to its output terminal internally. Consequently, the very last slot having a plugged-in memory module can be automatically connected to a terminal device, thereby forming a complete signaling channel for the transmission of data and clock pulses. Since empty slots can be automatically detected, there is no need to plug in dummy memory modules.
By providing a simple controlling circuit in the memory controlling system, the terminal device of this system can be connected to the very last slot having a plugged-in memory. Hence, a complete signal transmission channel is established. Therefore, cost of production can be reduced, and the product can be more competitive in the market.
In addition, there is no need to plug dummy memory modules into empty slots. Furthermore, users are free to add memory modules into empty slots or dismantle some memory modules from the memory slots without the need to worry about putting back a terminal device in the very last, memory-occupied slot. This is because not only is the correct slot for connecting with a terminal device automatically determined, but the action of connecting the terminal device with the correct slot is carried out automatically as well.
It is to be understood that both the foregoing general description

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