Memory module and method for operating a memory module in a...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing

Reexamination Certificate

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C714S763000

Reexamination Certificate

active

10724135

ABSTRACT:
Memory modules based on DDR-DRAMs are provided with a buffer and error checking module, which integrates an error data memory and a buffer/redriver functionality for conditioning data signals that are transferred to the memory module and output from the memory module and is suitable for the correction of user data stored erroneously in the DDR-DRAMs. The buffer and error checking module enables the integration of both error correction and buffer/redriver functionality on memory modules within the restricted memory module dimensions in accordance with definitive industry standards, simplified or improved routing of data lines and of control and address lines and also, by virtue of a reduction of erroneously transferred data to the data memory system, an increased real data transfer rate.

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patent: 6092146 (2000-07-01), Dell et al.
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patent: 6421274 (2002-07-01), Yoshimura
patent: 6791877 (2004-09-01), Miura et al.
patent: 6832340 (2004-12-01), Larson et al.
“Achieving Fault Secureness in Parity Prediction Arithmetic Operators: General Conditions and Implementations” by Nicolaidis et al. in: European Design and Test Conference, 1996. ED&TC 96. Proceedings Publication Date: Mar. 11-14, 1996 pp. 186-193.
“A Highly Efficient Transparent Online Memory Test” by Thaller in the International Test Conference, 2001 Proceedings Publication Date: 2001 pp. 230-239.

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