Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2005-08-09
2005-08-09
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C714S735000, C365S201000
Reexamination Certificate
active
06928593
ABSTRACT:
A memory component with built-in self test includes a memory array. An input/output interface is coupled to the memory array and has a loopback. A controller is provided to transmit memory array test data to the memory array to store the memory array test data, and to read the memory array test data from the memory array. A compare register is also provided to compare the memory array test data transmitted to the memory array with the memory array test data read from the memory array.
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Bonella Randy M.
Halbert John
De'cady Albert
Gandhi Dipakkumar
Intel Corporation
Pillsbury & Winthrop LLP
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