Static information storage and retrieval – Read/write circuit – Testing
Reexamination Certificate
2000-07-21
2003-02-04
Zarabian, A. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Testing
C365S189080
Reexamination Certificate
active
06515922
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a memory module including a multiplicity of memory devices such as SDRAMs (Synchronous Dynamic Random Access Memories) formed on a substrate.
2. Description of the Background Art
FIG. 13
shows a background art memory module. The memory module MMc of
FIG. 13
comprises eight memory devices MD
0
to MD
7
formed on a memory module substrate. A memory device, as that term is used herein, is a storage element in the form of a chip. As an example, eight data lines DQ
0
to DQ
7
are connected to the memory device MD
0
, and data lines DQ
8
to DQ
15
are connected to the memory device MD
1
. Likewise, data lines are connected to each of the other memory devices MD
2
to MD
7
. The data lines DQ
0
to DQ
63
serve as transmission paths for transmitting and receiving data to and from a portion external to the memory module MMc during a memory operation such as bit-wise writing and reading of data into and from a memory cell in each of the memory devices MD
0
to MD
7
and a refresh operation. The memory devices MD
0
to MD
7
are also connected to signal lines, not shown, for transmitting operating signals such as a write enable signal and an address signal for the memory operation in addition to the data lines DQ
0
to DQ
63
.
Thus, the memory module has such a large number of signal lines for connection to the memory devices, and these signal lines are connected to the external portion through I/O pins provided on the memory module substrate.
Memory modules, after being manufactured, are generally inspected by some tests such as an electrical assembly check for judging whether or not interconnect lines are formed well, a data write and read operation test, and a memory content retention operation check.
However, the increased number of I/O pins of the memory module as above described has required an expensive tester having a great number of I/O pins even when the electrical assembly check and the simple data write and read operation test (e.g., a write operation which applies “1” or “0” to all data lines and a subsequent read operation) are performed. The tester having a great number of I/O pins is expensive since the tester includes a data write driver and a data read comparator for each of the I/O pins.
Thus, there arises a need for a memory module which allows an inexpensive tester to carry out the electrical assembly check and the simple data write and read operation test on the memory devices.
A technique for conducting the above described tests on a single memory device, rather than the memory module, is disclosed in, for example, Japanese Patent Application Laid-Open Nos. P61-261895A and P61-292300A (1986).
FIG. 14
shows a technique disclosed in Japanese Patent Application Laid-Open No. P61-261895A. In this technique, data lines
111
establish connection between a memory array
101
and a multiplexer
102
, and data from the memory array
101
is outputted through the multiplexer
102
. An output from the multiplexer
102
is outputted through a switching circuit
103
for switching between the memory operation and a testing operation, an output buffer
104
and an output pad
105
to an external portion. An exclusive OR circuit
106
is also connected to the memory array
101
through data lines
112
. The exclusive OR circuit
106
conducts tests on the memory array
101
.
Operation in this technique is described below. In the memory operation, a signal &phgr;
1
inputted to the switching circuit
103
is “0,” and the output from the multiplexer
102
is applied to the output buffer
104
independently of an output from the exclusive OR circuit
106
.
In the testing operation, on the other hand, the signal &phgr;
1
inputted to the switching circuit
103
is “1.” The same 1-bit data (e.g., “1”) is written into all memory cells to be tested in the memory array
101
. The exclusive OR circuit
106
receives a 1-bit data signal &phgr;
2
which is the same as the data written into the memory array
101
and outputs from the data lines
112
to perform an exclusive OR operation thereon.
In the event of imperfect interconnect formation or a data read and write malfunction in the memory array
101
, there is a high possibility that data other than “1” appears on one of the data lines
112
. Therefore, the memory array
101
is judged as being normal when the output from the exclusive OR circuit
106
is “0,” i.e., all inputs to the exclusive OR circuit
106
are the same 1-bit data. On the other hand, the memory array
101
is judged as being defective when the output from the exclusive OR circuit
106
is “1.” In this manner, whether the memory device is good or not is examined.
The use of this technique allows an inexpensive tester including a single comparator to conduct the electrical assembly check and the simple data write and read operation test on the memory device.
This technique may be applied to a memory module to accomplish the memory module on which an inexpensive tester can conduct the above described tests. Specifically, the memory device shown in
FIG. 14
may be used as a device to be mounted in the memory module.
However, simply mounting this memory device into the memory module is not sufficient, but it is necessary that output signals TMS
0
to TMS
7
are outputted from the memory devices MD
0
to MD
7
, respectively, as in a memory module MMd shown in
FIG. 15
, for example. Thus, there is a limit to the use of an inexpensive tester having a smaller number of I/O pins.
Additionally, a testing circuit provided in a memory device as in the above described technique is not always capable of conducting perfect tests since, in some tests, the signals from the memory array
101
bypass a circuit through which those signals pass during the memory operation. For instance, since the multiplexer
102
is bypassed during the testing operation in the arrangement shown in
FIG. 14
, it is impossible to test the entire device including the operation of the multiplexer
102
.
Further, the direct connection of the exclusive OR circuit
106
to test to the memory array
101
as in the memory device shown in
FIG. 14
causes an input load of the exclusive OR circuit
106
to be imposed on the memory array
101
during the memory operation, thereby requiring an additional driving capability when the memory array
101
outputs data. Moreover, signal reflection is prone to occur on the data lines
111
, resulting in deterioration of data I/O characteristics.
The provision of the testing circuit in the memory device presents another problem of increasing the chip size of the memory device itself, resulting in increased costs.
The technique disclosed in Japanese Patent Application Laid-Open No. P61-292300A (1986) has similar problems.
SUMMARY OF THE INVENTION
According to a first aspect of the present invention, a memory module comprises: at least one memory device connected to at least one data line for bit-wise transmitting and receiving data to and from an external portion; an exclusive OR element having at least one input corresponding to the at least one data line; and at least one switch for connecting the at least one data line to the external portion and the at least one input of the exclusive OR element, wherein the at least one switch receives a first instruction for causing the at least one switch to connect the at least one data line to the at least one input of the exclusive OR element in a testing operation and causing the at least one switch to connect the at least one data line to the external portion in a memory operation.
Preferably, according to a second aspect of the present invention, in the memory module of the first aspect, in the testing operation, common 1-bit data is applied to the at least one data line and stored in the at least one memory device before the first instruction causes the at least one switch to connect the at least one data line to the at least one input of the exclusive OR element, and thereafter whether the at least one memory device malfunctions o
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