Memory modeling circuit with fault toleration

Details Memory modeling circuit with fault toleration Memory modeling circuit with fault toleration

2008-01-08

2008-01-08

Iqbal, Nadeem (Department: 2114)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

C714S054000, C714S797000

Reexamination Certificate

active

07318175

ABSTRACT:
A memory modeling circuit with fault toleration includes a compare circuit, a control circuit and a test circuit. The compare circuit receives the data stored in the same address of memories and compares data with each other to produce the correct reading data. The control circuit connects with the control signals of the memories and detects that control signals. The control circuit has data output/input ports. When the control signal of the memories is to write, the control circuit enters a writing mode and writes the writing data received from the data output/input ports in the same address of the memories. When the control signal of the memories is to read, the control circuit enters a reading mode, receiving the reading data generated by the compare circuit and outputs it through the data output/input ports. The test circuit receives the data stored in the same address of the memories and the reading data generated by the compare circuit to generate a testing result. The testing result can identify a faulty memory or a faulty compare circuit.

REFERENCES:
patent: 4375683 (1983-03-01), Wensley
patent: 4628509 (1986-12-01), Kawaguchi
patent: 4794601 (1988-12-01), Kikuchi
patent: 5757809 (1998-05-01), Kiso et al.
patent: 6009026 (1999-12-01), Tamlyn et al.
patent: 6957371 (2005-10-01), Ricchetti et al.
patent: 7013414 (2006-03-01), Takeshige et al.
patent: 7047455 (2006-05-01), Roohparvar
patent: 7137050 (2006-11-01), Merritt et al.
patent: 2003/0204797 (2003-10-01), Lin
patent: 06150698 (1994-05-01), None

Affiliated with

Also associated with

Rating

Memory modeling circuit with fault toleration does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Memory modeling circuit with fault toleration, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory modeling circuit with fault toleration will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2812806