Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-11-26
2003-12-09
Prenty, Mark V. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S768000
Reexamination Certificate
active
06661064
ABSTRACT:
BACKGROUND AND SUMMARY OF THE INVENTION
The present application relates to integrated circuit memory chips, and particularly to chips which include low-power SRAM cells.
Sheet Resistance and Clock Speed
The patterned thin-film layers which are used for conduction in integrated circuit devices will typically have a very significant distributed resistance and capacitance, which imposed a significant time constant on signals routed through such layers.
The RC time constant of the gate can be reduced by making metal contact to the gate in more places. This effectively reduces the “R” term in the time constant. However, each such contact consumes some gate area. Moreover, in single-level-metal processes, the requirements of making source contacts severely constrain the possible geometries for gate contacts.
Silicides and Conductive Nitrides
One general technique for improving the conductivity of silicon and polysilicon layers is to clad them with a metal silicide and/or a conductive nitride (usually TiN). Many different metal suicides have been proposed for use; among the most common are titanium, cobalt, tantalum, tungsten, nickel, and molybdenum silicide.
One particularly convenient way to provide suicides is to use a self-aligned process, in which a metal is deposited overall and heated to react it with exposed silicon. The unreacted metal can then be stripped off. Such process are known as “saliciding.”
Salicidation is not without costs and risks. With shallow source/drain depths, salicidation may lead to increased leakage. The potential problems are reviewed, for example, in S. Wolf, II SILICON PROCESSING FOR THE VLSI ERA at 142-152 (1990). Thus silicidation is often avoided in high-density low-power memories.
Innovative Structures and Methods
The disclosed inventions provide an integrated circuit memory fabrication process and structure, in which salicidation is performed on the periphery (and optionally on the ground lines) of a memory chip, but not on the transistors of the memory cells. This avoids leakage in the array, while preserving maximal speed in the peripheral logic.
This is advantageously, but not necessarily, used in combination with the sidewall nitride process disclosed in the parent application, which provides a self-aligned zero-offset contact process.
REFERENCES:
patent: 4080719 (1978-03-01), Wilting
patent: 4102733 (1978-07-01), De La Moneda et al.
patent: 4128670 (1978-12-01), Gaensslen
patent: 4253907 (1981-03-01), Parry et al.
patent: 4354896 (1982-10-01), Hunter et al.
patent: 4356623 (1982-11-01), Hunter
patent: 4384938 (1983-05-01), Desilets et al.
patent: 4398335 (1983-08-01), Lehrer
patent: 4443930 (1984-04-01), Hwang et al.
patent: 4470189 (1984-09-01), Roberts et al.
patent: 4543271 (1985-09-01), Peters
patent: 4622735 (1986-11-01), Shibata
patent: 4654112 (1987-03-01), Douglas
patent: 4656732 (1987-04-01), Teng et al.
patent: 4657628 (1987-04-01), Holloway et al.
patent: 4660278 (1987-04-01), Teng
patent: 4675073 (1987-06-01), Douglas
patent: 4686000 (1987-08-01), Heath
patent: 4707218 (1987-11-01), Giammarco et al.
patent: 4715109 (1987-12-01), Bridges
patent: 4721548 (1988-01-01), Morimoto
patent: 4755476 (1988-07-01), Böhm et al.
patent: 4788160 (1988-11-01), Havemann et al.
patent: 4792534 (1988-12-01), Tsuji et al.
patent: 4801350 (1989-01-01), Mattox et al.
patent: 4801560 (1989-01-01), Wood et al.
patent: 4810666 (1989-03-01), Taji
patent: 4818335 (1989-04-01), Karnett
patent: 4824767 (1989-04-01), Chambers et al.
patent: 4841481 (1989-06-01), Ikeda et al.
patent: 4894351 (1990-01-01), Batty
patent: 4912061 (1990-03-01), Nasr
patent: 4962414 (1990-10-01), Liou et al.
patent: 4986878 (1991-01-01), Malazgirt et al.
patent: 4988423 (1991-01-01), Yamamoto et al.
patent: 4994402 (1991-02-01), Chiu
patent: 4996167 (1991-02-01), Chen
patent: 5003062 (1991-03-01), Yen
patent: 5010032 (1991-04-01), Tang et al.
patent: 5027185 (1991-06-01), Liauh
patent: 5030585 (1991-07-01), Gonzalez et al.
patent: 5059554 (1991-10-01), Spinner et al.
patent: 5061646 (1991-10-01), Sivan et al.
patent: 5063176 (1991-11-01), Lee et al.
patent: 5072275 (1991-12-01), Vora
patent: 5110763 (1992-05-01), Matsumoto
patent: 5117273 (1992-05-01), Stark et al.
patent: 5158910 (1992-10-01), Cooper et al.
patent: 5166088 (1992-11-01), Ueda et al.
patent: 5174858 (1992-12-01), Yamamoto et al.
patent: 5200808 (1993-04-01), Koyama et al.
patent: 5214305 (1993-05-01), Huang et al.
patent: 5244841 (1993-09-01), Marks et al.
patent: 5250472 (1993-10-01), Chen et al.
patent: 5254867 (1993-10-01), Fukuda et al.
patent: 5256895 (1993-10-01), Bryant et al.
patent: 5260229 (1993-11-01), Hodges et al.
patent: 5262344 (1993-11-01), Mistry
patent: 5266516 (1993-11-01), Ho
patent: 5266525 (1993-11-01), Morozumi
patent: 5283449 (1994-02-01), Ooka
patent: 5286674 (1994-02-01), Roth et al.
patent: 5310720 (1994-05-01), Shin et al.
patent: 5320983 (1994-06-01), Ouellet
patent: 5321211 (1994-06-01), Haslam et al.
patent: 5323047 (1994-06-01), Nguyen
patent: 5380553 (1995-01-01), Loboda
patent: 5395784 (1995-03-01), Lu et al.
patent: 5411917 (1995-05-01), Forouhi et al.
patent: 5439846 (1995-08-01), Nguyen et al.
patent: 5444018 (1995-08-01), Yost et al.
patent: 5486712 (1996-01-01), Arima
patent: 5736421 (1998-04-01), Shimomura et al.
patent: 6051864 (2000-04-01), Hodges et al.
patent: 6514811 (2003-02-01), Hodges et al.
patent: 41 02 422 (1991-08-01), None
patent: 0 111 706 (1984-06-01), None
patent: 0 185 787 (1986-07-01), None
patent: 0 071 029 (1987-11-01), None
patent: 0 265 638 (1988-05-01), None
patent: 0 327 412 (1989-08-01), None
patent: 0 491 408 (1992-06-01), None
patent: 0 523 856 (1993-01-01), None
patent: 0 534 130 (1993-03-01), None
patent: 2 077 993 (1981-12-01), None
patent: 2 083 948 (1982-03-01), None
patent: 2 106 315 (1983-04-01), None
patent: 2 167 901 (1986-06-01), None
patent: 56-8846 (1981-01-01), None
patent: 56-164578 (1981-12-01), None
patent: 60-58635 (1985-04-01), None
patent: 60-246675 (1985-12-01), None
patent: 61-26240 (1986-02-01), None
patent: 61-232646 (1986-10-01), None
patent: 62-106645 (1987-05-01), None
patent: 63-293946 (1988-11-01), None
patent: 64-82653 (1989-03-01), None
patent: 01264257 (1989-10-01), None
patent: 2-192724 (1990-07-01), None
patent: 3133131 (1991-06-01), None
patent: 4-92453 (1992-03-01), None
patent: 5-74958 (1993-03-01), None
patent: 5-82751 (1993-04-01), None
patent: 5-107270 (1993-04-01), None
patent: 5-267477 (1993-10-01), None
Wehner, et al., “The Nature of Physical Sputtering,” Handbook of Thin Film Technology, p. 3-1 through 3-38, McGraw-Hill (1970).
Gambino, et al., “A Si3N4Etch Stop Process for Borderless Contacts in 0.25 &mgr;m Devices,” VMIC Conference, 1995, pp. 558-564.
Singer, “A New Technology for Oxide Contact and Via Etch,” Semiconductor Int'l, p. 36 (1993).
Jones, N.J., et al., “Salicide With Buried Silicide Layer,” IBM Technical Disclosure Bulletin, 27 (2), Jul. 1984, pp. 1044-1045.
Wolf, et al., “Silicon Processing for the VLSI Era,” vol. 1, Lattice Press, 1986, pp. 182-185.
Murarka, S.P., “Silicides for VLSI Applications,” 1983, Academic Press, pp. 164-167.
H.T.G. Hentzell, et al., “Formation of Aluminum Silicide Between Two Layers of Amorphous Silicon,” Applied Physics Letters, vol. 50, No. 14, pp. 933-934, 4/87.
M. Lin, et al., “An Environment-Insensitive Trilayer Structure for Titanium Silicide Formation,” Journal of Electrochem. Soc., vol. 133, No. 11, pp. 2386-2389, 11/86.
S. Saitoh, et al., “Formation of a Double-Hetero Si/CoSi2/Si Structure Using Molecular Beam and Soid Phase Epitaxies,” Jap. Jour. of Applied Physics, vol. 20, pp. 49-54, 1981.
J.K. Howard, “High Conductivity Transition Metal Silicide (Nbsi2) for FET Gate Structures,” IBM Technical Joirnal, vol. 22, No. 2, 7/79, pp. 598-599.
IBM Technical Disclosure Bulletin: “Dual Self-Aligned Silicides on FET Gates and Junctions,” vol. 31, No. 7, Dec. 1988, p. 154.
IBM Technical Disclosure Bulletin: “Method to Produce Sizes in Openings in Photo Images Smaller Than Lithographic Minimum Size,” vol. 29, No. 3, 1986, p. 1328.
Ishigaki, et al., “Low
Hodges Robert Louis
Nguyen Loi Ngoc
Jorgenson Lisa K.
Munck William A.
Prenty Mark V.
STMicroelectronics Inc.
LandOfFree
Memory masking for periphery salicidation of active regions does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Memory masking for periphery salicidation of active regions, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory masking for periphery salicidation of active regions will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3158131