Memory masking for periphery salicidation of active regions

Details Memory masking for periphery salicidation of active regions Memory masking for periphery salicidation of active regions

1997-07-14

2000-04-18

Jackson, Jr., Jerome

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257369, 257754, 257296, H01L 2978, H01L 2945

Patent

active

060518642

ABSTRACT:
An integrated circuit memory fabrication process and structure, in which salicidation is performed on the periphery (and optionally on the ground lines) of a memory chip, but not on the transistors of the memory cells.

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