Memory mapping method and apparatus to fold sparsely populated s

Details Memory mapping method and apparatus to fold sparsely populated s Memory mapping method and apparatus to fold sparsely populated s

1995-06-07

1997-11-25

Lane, Jack A.

Electronic digital logic circuitry

Multifunctional or programmable

Array

39549701, 326 39, G06F 1206

Patent

active

056921470

ABSTRACT:
A field programmable gate array has a plurality of programmable resources addressable per respective x and y dimensions of an x,y two dimensional array. A memory device provides a plurality of memory units that store configuration data for configuring associated programmable resources of the field programmable gate array. A controller addresses the memory device with an N-bit address for retrieving given configuration data. An address decoder and sequencer divides the N-bit address into first, second, and third portions and employs the first and third portions interchangeably, in accordance with the second portion, for addressing respective x and y dimensions of the plurality of programmable resources for selecting an associated programmable resource to be configured in accordance with the retrieved configuration data.

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T. A. Kean, PCT Patent Application WO 94/10754, filed Nov. 5, 1993, entitled "Improved Configurable Cellular Array".

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