Electrical computers and digital processing systems: memory – Address formation – Address mapping
Reexamination Certificate
2007-06-19
2007-06-19
Nguyen, T (Department: 2187)
Electrical computers and digital processing systems: memory
Address formation
Address mapping
C711S205000, C711S206000
Reexamination Certificate
active
10723044
ABSTRACT:
A method of performing memory mapped input output operations to an alternate address space comprising: establishing a first instruction directed to a first memory mapped input output alternate address space associated with an adapter to store data in accordance with a definition of a z/Architecture; establishing a second instruction directed to the first memory mapped input output alternate address space associated with an adapter to load data in accordance with the definition(s) of the z/Architecture; and wherein a process issues at least one of the first instruction and the second instruction and thereby causes execution of at least one of the store and load with the first alternate address space.
REFERENCES:
patent: 5721858 (1998-02-01), White et al.
patent: 6061757 (2000-05-01), Arimilli et al.
patent: 6212592 (2001-04-01), Klein
patent: 6442634 (2002-08-01), Bronson et al.
patent: 6442635 (2002-08-01), Brightman et al.
patent: 6598144 (2003-07-01), Bailey et al.
patent: 6742075 (2004-05-01), Bailey et al.
patent: 7003586 (2006-02-01), Bailey et al.
patent: 2002/0165897 (2002-11-01), Kagan et al.
patent: 2003/0188062 (2003-10-01), Luse et al.
patent: 2004/0030854 (2004-02-01), Qureshi et al.
patent: 9069072 (1997-03-01), None
Formal Properties of Recursive Virtual Machine Architectures. Gerald Balpaire* New York University and Nai-Ting Hsu* University of Wisconsin .* Department of Computer Science, Courant Institute of Mathematical Sciences. This work is supported by ERDA under contract E(11-1)-3077. ** Computer Sciences Department and Mathematics Research Center. This work is supported in part by the US Army contract DAHCO4-75-C-0024. pp. 89-96, no date.
Daisy: Dynamic Compilation for 100% Architectural Compatibility. Kenak Ebcioglu and Erik R. Altman. IBM Thomas J. Watson Research Center, Yorktown Heights, NY 10598. {kemal,erik}@watson.ibm.com. 1997 ACM 0-89791-901-7/97/0006 . . . $3.50 pp. 26-37.
Emulation—A Useful Tool in the Development of Computer Systems. F.A. Salomon and D.A. Tafuri. Bell Laboratories, Naperville, IL Annual Simulation symposium. pp. 55-71, no date.
IBM Technical Disclosure Bulletin. vol. 38 No. 07 Jul. 1995. Emulating Memory Mapped File Input/Output on OS/2. pp. 505-507.
Design Challenges of Virtual Networks: Fast, General-Purpose Communication. Alan M. Mainwaring, Computer Science Division, University of California at Berkely. Berkeley, CA 94720-1776 and David E. Culler, Computer Science Division, University of California at Berkeley. Berkeley, CA 94720-1776. May 1999 Atlanta, GA, USA. 1999 ACM 1-58113-100-3/99/0004 . . . $5.00.
U.S. Appl. No. 10/723,506, filed Nov. 25, 2003, Craddock et al.
U.S. Appl. No. 10/723,405, filed Nov. 25, 2003, Brice et al.
Errickson Richard K.
Farrell Mark S.
Gainey, Jr. Charles W.
Gregg Thomas A.
Hernandez Carol B.
Cantor & Colburn LLP
International Business Machines - Corporation
Nguyen T
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