Electrical computers and digital data processing systems: input/ – Input/output data processing – Peripheral configuration
Reexamination Certificate
2006-04-18
2010-06-01
Dang, Khanh (Department: 2111)
Electrical computers and digital data processing systems: input/
Input/output data processing
Peripheral configuration
C710S305000, C710S313000
Reexamination Certificate
active
07730227
ABSTRACT:
A mechanism and method for redefining an application specific integrated circuit's I/O bus structure in real-time. The mechanism includes an address map block, a state machine block, and a bus arbitration block. At initialization, the address map is configured to divide the address space into regions and type of bus structure. When an I/O access is requested by a client (e.g., CPU, DMA controller, etc.), the request is mapped into a region and type of bus structure by the address map block. The region and type of bus structure is used by the state machine. The state machine determines the syntax and protocol for the region and type of bus. The state machine signals the bus arbitration block to grant I/O bus ownership when it is available. Once ownership is granted, I/O bus pins are defined and access is granted.
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Definition of “Real Time” by Wikipedia, the free Encyclopedia.
Broadcom Corporation
Dang Khanh
Sterne Kessler Goldstein & Fox P.L.L.C.
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