Memory management to enable memory deep power down mode in...

Details Memory management to enable memory deep power down mode in... Memory management to enable memory deep power down mode in...

2007-09-18

2007-09-18

Perveen, Rehana (Department: 2116)

Electrical computers and digital processing systems: support

Computer power control

Power conservation

C711S165000

Reexamination Certificate

active

10932711

ABSTRACT:
An apparatus and method is disclosed for reducing power consumption in a computing system by moving pages allocated in real memory portions to other real memory portions. When a real memory portion contains no pages, that memory portion can be put into a Deep Power Down (DPD) state that has lower power consumption than when that memory portion is in normal operation. The computing system can also be aware of power consumption of each real memory portion, and, with such awareness, the invention teaches consolidation of pages from real memory portions having relatively higher power consumption to real memory portions having relatively lower power consumption.

REFERENCES:
patent: 5036493 (1991-07-01), Nielsen
patent: 6141283 (2000-10-01), Bogin et al.
patent: 6462364 (2002-10-01), Horiuchi
patent: 6721223 (2004-04-01), Matsumoto et al.
patent: 7010656 (2006-03-01), Gupta

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