Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing
Reexamination Certificate
2005-08-02
2005-08-02
Anderson, Matthew D. (Department: 2189)
Electrical computers and digital processing systems: memory
Storage accessing and control
Access timing
C711S200000, C711S202000, C711S203000, C711S206000, C711S207000, C711S209000, C711S102000, C711S103000
Reexamination Certificate
active
06925542
ABSTRACT:
Memory management in a data processing system (10) is achieved by using one or more timing bits (54) to specify a timing parameter of a memory (18, 19, 34). To implement this in some embodiments of the present invention, a memory array (32, 33, 42) is multiple-mapped in the physical memory map (70) of processor (12) and the address bits (54) associated with the multiple-mapping are used to directly control timing parameters of the memory arrays (32, 33, 42). This allows for flexible timing specifications to be derived quickly on an access by access basis without requiring any additional control storage overhead.
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Marshall Ray
Moyer William C.
Anderson Matthew D.
Freescale Semiconductor Inc.
Hill Susan C.
King Robert L.
Li Zhuo H.
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