Memory management for a symmetric multiprocessor computer...

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories

Reexamination Certificate

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Reexamination Certificate

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07085897

ABSTRACT:
A modular multiprocessor computer system having a plurality of nodes each being in communication with each other via communication links. The plurality of nodes each have local memory and local cache accessible by the other nodes. The plurality of nodes each also having a cache directory, one or more processing units, and a memory coherent directory to keep track of the scope of ownership of data within the modular multiprocessing computer system. The local memory and the local cache contain configurable regions of storage, wherein memory coherency traffic on the communication links between the nodes is controlled through the use of the memory coherent directory during a data request.

REFERENCES:
patent: 4037209 (1977-07-01), Nakajima et al.
patent: 4511964 (1985-04-01), Georg et al.
patent: 4811216 (1989-03-01), Bishop et al.
patent: 4855903 (1989-08-01), Carleton et al.
patent: 4980822 (1990-12-01), Brantley, Jr. et al.
patent: 5093913 (1992-03-01), Bishop et al.
patent: 5123106 (1992-06-01), Otsuki et al.
patent: 5228127 (1993-07-01), Ikeda et al.
patent: 5269013 (1993-12-01), Abramson et al.
patent: 5428803 (1995-06-01), Chen et al.
patent: 5560027 (1996-09-01), Watson et al.
patent: 5710907 (1998-01-01), Hagersten et al.
patent: 5727150 (1998-03-01), Laudon et al.
patent: 5784697 (1998-07-01), Funk et al.
patent: 5787468 (1998-07-01), Clark
patent: 5887138 (1999-03-01), Hagersten et al.
patent: 5893144 (1999-04-01), Wood et al.
patent: 5895487 (1999-04-01), Boyd et al.
patent: 5926829 (1999-07-01), Hagersten et al.
patent: 5931938 (1999-08-01), Drogichen et al.
patent: 5999712 (1999-12-01), Moiin et al.
patent: 6038651 (2000-03-01), Van Huben et al.
patent: 6167437 (2000-12-01), Stevens et al.
patent: 6205528 (2001-03-01), Kingsbury et al.
patent: 6289424 (2001-09-01), Stevens
patent: 6336177 (2002-01-01), Stevens
patent: 6505286 (2003-01-01), Kingsbury et al.
patent: 6874053 (2005-03-01), Yasuda et al.
patent: 6901485 (2005-05-01), Arimilli et al.
patent: 2002/0083149 (2002-06-01), Van Huben et al.
patent: 2002/0083243 (2002-06-01), Van Huben et al.
patent: 2002/0083299 (2002-06-01), Van Huben et al.
patent: 2003/0009634 (2003-01-01), Arimilli et al.
patent: 2003/0009639 (2003-01-01), Arimilli et al.
patent: 2003/0009640 (2003-01-01), Arimilli et al.
patent: 2003/0009641 (2003-01-01), Arimilli et al.
US 6,021,479, 02/2000, Stevens (withdrawn)
Culler et al. “Parallel Computer Architecture”, 1999, Morgan Kaufmann, p. 553-560.

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