Memory management device

Electrical computers and digital processing systems: memory – Address formation – Address mapping

Reexamination Certificate

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Details

C711S151000, C711S166000

Reexamination Certificate

active

08060723

ABSTRACT:
A second memory stores data in units of segments. An assignment control circuit sets up a buffer space as a logical address space. A buffer space is formed as a set of at least one segment. A state storage circuit stores association between a buffer space and segments as segment assignment information. An address conversion circuit refers to segment assignment information to convert a logical address into a physical address. A segment queue stores a free segment and a buffer queue stores a free buffer. The state storage circuit includes a plurality of register groups each of which includes a plurality of segment registers. A register group is associated with one of the plurality of buffer spaces. A range number identifying a range of logical addresses in the associated buffer space is set up in a segment register.

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International Search Report, International application No. PCT/JP2007/050131, Japanese Patent Office, May 22, 2007.
International Preliminary Report on Patentability and Written Opinion of the International Searching Authority, International application No. PCT/JP2007/050131, The International Bureau of WIPO, Jul. 14, 2009.

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