Electrical computers and digital processing systems: memory – Storage accessing and control – Memory configuring
Reexamination Certificate
1999-08-16
2002-12-03
Kim, Matthew (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Memory configuring
C711S147000, C711S154000, C710S020000, C710S023000, C710S065000
Reexamination Certificate
active
06490669
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a memory LSI with a compressed data inputting and outputting function. More particularly, the invention relates to a large capacity semiconductor memory LSI (Large Scale Integrated circuit) to be used for forming a main memory system or a graphic memory system in a computer system, such as a dynamic random access memory (DRAM).
2. Description of the Related Art
In general, in a computer system constituted of a central processing unit (CPU) and a semiconductor memory LSI, a passband width of the semiconductor LSI is required to be greater associating with improvement of performance of CPU.
Therefore, particularly in case of DRAM which has longer access period in comparison with other memory LSI, technical development has been actively performed in order to improve passband width. Here, the passband width represents a data transfer performance which is designed by a product of number of signal lines to be used in data transfer and its operation frequency.
A technology to be typically employed for improving the passband of the semiconductor memory LSI is for improving operation frequency of an external interface. Currently, as the maximum passband width of DRAM, an interface technology for DRAM has realized about 600 Mbits per second per signal line.
However, due to disturbance of signal waveform caused by offset of timing between the signal lines or inconsistency of impedance of the bus, or due to external noise, switching noise or so forth, significant difficulty should be encountered in further improvement of the operation frequency.
In this circumstance, it becomes difficult to improve the passband width by simply improving the operation frequency of the external interface as in the prior art. Therefore, there has been presented a proposal to reduce a data transfer amount by compressing data to be transferred and thus equivalently improve the passband width.
Such proposal has been seen in Steven A. Przzybylski, “New DRAM Technologies”, Second Edition, MicroDesign Resources, 1996, pp 124 to 127, for example.
In this technology, as shown in
FIG. 5
, two storage regions of a storage region
54
for a drawing data in non-compressed condition and a storage region
53
for a drawing data in compressed condition are provided in a frame buffer
52
.
These regions are consisted of an aggregate of blocks corresponding to given regions on a display, respectively. On the other hand, each block in the compressed drawing data storage region
53
is provided with a marker indicative whether the data in the block is effective or null.
Upon drawing one block, a graphic controller
51
at first makes reference to the compressed drawing data in the relevant block. If the drawing data in the relevant block in the compressed drawing data storage region is effective, the graphic controller
51
performs drawing of the block on the display using the compressed drawing data. If the drawing data in the relevant block in the compressed drawing data storage region is null, the graphic controller
51
performs drawing of the block on the display using the non-compressed drawing data in the corresponding block of the non-compressed drawing data storage region
54
.
In the latter case, the graphic controller
51
compresses the read out block of the non-compressed drawing data and writes in the thus compressed drawing data in the corresponding block of the compressed drawing data storage region
53
the frame buffer. Also, the graphic controller
51
gives the marker indicative that the written compressed drawing data is effective.
Upon rewriting the drawing data by the graphic controller
51
, the drawing data is written in the non-compressed drawing data storage region
54
. At this time, the block in the compressed drawing data storage region
53
corresponding to the rewritten block is then marked as null. Here, it should be noted that the frame buffer is a memory region to be used to be particularly for drawing display image.
The data transfer amount required for drawing display image can be significantly reduced through the following procedure. In the foregoing technology, nothing has been mentioned particularly for compression method of the drawing data. As compression method of the data having redundancy or regularity has been discussed in Terry A. Welch, “A Technique for High-Performance Data Compression”, IEEE Computer, June, 1984, pp 8-19. The method discussed may be realized either by software or hardware.
On the other hand, how much data transfer amount can be reduced by such technology is variable depending upon the compression method and/or kind of the image data. However, it is typically expected that the transfer data amount can be reduced to be one half to one tenth.
In the foregoing conventional semiconductor memory LSI, data transfer amount required for drawing display image can be significantly reduced in comparison with the case where compression is not performed, by employing the data compression technology.
This technology encounters a problem in that reduction of the data transfer amount cannot be directly reflected to improvement of the effective passband width. In general, the memory LSI is fixed a period from issuance of an instruction from a memory controller to initiation of data transfer and to finishing of data transfer. This is for restricting vacant period where data is not transferred on a data bus to be minimum and thus for gaining the effective passband width of the data bus by scheduling use periods of the data bus in a lump by the memory controller.
However, since the data length of the compressed data is not fixed length, it becomes not possible to expand the passband width. In this case, when this scheduling method is employed regarding that the compressed data has fixed length, waste vacant period may be caused on the data bus for a period corresponding to the data amount reduced by data compression. Therefore, effective passband width is not expanded.
On the other hand, another problem is encountered in that it cannot compress data transfer other than that for drawing display image on a display screen. Namely, when data is to be written in the memory LSI, data transfer amount cannot be reduced. Therefore, when display image is rewritten frequently, the foregoing technology cannot be effective means.
Furthermore, when the compressed data is null, it becomes necessary to read out the drawing data from the memory LSI and thereafter, the compressed data has to be written in the memory LSI. Namely, in a certain period, wasteful data transfer is performed for writing of the compressed data between the memory LSI and the graphic control LSI. Therefore, when rewriting of the display image is frequent, effective passband width becomes small. Therefore, the foregoing technology cannot be effective means.
SUMMARY OF THE INVENTION
Therefore, it is an object of the present invention to provide a memory LSI with a compression data input and output function which can reduce data transfer amount and can expand effective passband width by restricting transfer loss upon transfer of variable length compression data.
According to one aspect of the present invention, a memory LSI with compressed data input and output function including a memory cell array performing writing and reading of data with an external device, comprises:
input and output means for performing data transfer with the external device in compressed form of data;
detecting means for detecting a size of the compressed data on the basis of a compression information added to the compressed data and indicative of size of data after compression; and
means for operating at least an internal circuit including the memory cell array and the input and output means for a period necessary for transferring the compressed data depending upon a result of detection by the detecting means.
The memory LSI with compressed data input and output function includes writing means for operating the internal circuit operates the internal circu
Chace Christian P.
Kim Matthew
Whitham Curtis & Christofferson, P.C.
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