Memory latency of processors with configurable stride based...

Details Memory latency of processors with configurable stride based... Memory latency of processors with configurable stride based...

2008-03-18

2008-03-18

Sparks, Donald (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S122000, C711S125000, C712S207000

Reexamination Certificate

active

07346741

ABSTRACT:
A method and apparatus for retrieving instructions to be processed by a microprocessor is provided. By pre-fetching instructions in anticipation of being requested, instead of waiting for the instructions to be requested, the latency involved in requesting instructions from higher levels of memory may be avoided. A pre-fetched line of instruction may be stored into a pre-fetch buffer residing on a microprocessor. The pre-fetch buffer may be used by the microprocessor as an alternate source from which to retrieve a requested instruction when the requested instruction is not stored within the first level cache. The particular line of instruction being pre-fetched may be identified based on a configurable stride value. The configurable stride value may be adjusted to maximize the likelihood that a requested instruction, not present in the first level cache, is present in the pre-fetch buffer. The configurable stride value may be updated manually or automatically.

REFERENCES:
patent: 6556952 (2003-04-01), Magro
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patent: 2003/0221069 (2003-11-01), Azevedo et al.
patent: 2004/0123043 (2004-06-01), Rotithor et al.
patent: 2005/0071572 (2005-03-01), Nakashima et al.
patent: 2006/0053256 (2006-03-01), Moyer et al.

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