Memory latency compensation

Details Memory latency compensation Memory latency compensation

1998-08-20

2002-02-26

Kim, Matthew (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Access timing

C711S003000

Reexamination Certificate

active

06351793

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention generally relates to a compensation of latency effects on memories.
Computer systems generally comprise more or less complex memory units for storing information, such as data or programs (sequences of instructions), on a temporary or permanent basis. The term ‘memory’ as used herein shall refer to any storage device such as disks, tapes, semiconductor devices, or the like, and is not limited to a certain type of purposes or applications such as in microcomputers. The term ‘data’ as used herein shall refer to any kind of information such as individual or collective data, programs, instructions, as well on a temporary or permanent basis.
An access onto a memory is normally composed of three basic operations: 1) Telling the memory what to do, for example, read a number of bytes from a location in the memory; 2) waiting for the memory to complete an access; and 3) receiving the read out data or writing data into the memory. The transfer at the system level can be broken down to three timing parameters: (a) address transport, (b) data access time and (c) data transport. The address transport can be defined as the time required to get a new address and any control into an interface of the memory. This transport time generally is a function of the memory interface only. The data access time can be defined as the time to perform a data access, i.e. the time required for the memory to access a certain data from the internal memory array or core. The data transport can be defined as the time required to move the data from or to the memory and generally depends on the bandwidth, or signaling rate of the memory interface.
An important application of memories, and in particular deep memories (i.e. memories with a large memory capacity), is in testing applications for testing e.g. integrated circuits (IC's) or other electronic devices, such as the Hewlett-Packard HP 83000 Digital IC Test Systems. A typical testing unit comprises a tester circuit and a device under test (DUT), which can be an IC or any other electronic device. Details of such testing devices can e.g. be found in U.S. patent application Ser. No. 09/050,505, issued as U.S. Pat. No. 6,216,243, co-pending U.S. patent application Ser. No. 09/140,427, and in the issued U.S. Pat. Nos. 6,065,144 and 6,055,644, all of the same applicant. The tester circuit generally comprises a signal generating unit for generating and applying a stream of stimulus data to the DUT, a signal receiving unit for receiving a response on the stream of stimulus data from the DUT, and a signal analyzing unit for comparing the response with an expected data stream. Test data applied to the DUT is also called vector data or test vector and comprises one or more single individual vectors. Each individual vector may represent a signal state which is either to be applied at one or more inputs of the DUT or output by the DUT, at a given point in time. In a digital IC-Tester vectors are normally executed in a sequential stream with parts of varying length thereof being repeated a certain number of times.
In particular digital IC-testers have a growing need for fast and deep memory to store the test vectors that are necessary to stimulate the DUT and to evaluate its response. As the DUTs become more and more complex and have an increasing amount of gates to be tested, the vector sequences become accordingly huge. In order to provide those massive amounts of memory at a reasonable price, memory devices with a high memory density are usually used, which also allow for high vector rates to minimize the test execution time and also to be able to test the DUT at its intended operating speed. The memory technology with the highest memory density presently is the dynamic random access memory (DRAM) technology.
A general limitation of all memories is the so-called latency time, as the time interval between the instant at which an instruction control unit initiates a call for data and the instant at which the actual transfer of data begins, or in other words, the time needed to access the first data word at a random address. The latency time generally increases the data access time. The latency time is not a fixed value for a certain memory or type of memory, but depends on the actual data access. However, in most memories the latency time substantially is a constant value for most of the data accesses. For the sake of simplicity, the latency time shall be regarded the following as a constant value for a certain memory.
Although the physical time to internally access a certain type of memory might be the same, the differences between memory devices that may affect the latency time can be the speed at which an address and a (control) information can be moved to the memory device, and the speed at which data can be moved back to a controller.
In applications which require only sequential (or as a synonym: serial) accessing, such as reading or writing, onto memories, i.e. an access onto the memory (e.g. data is to be written into the memory) occurs sequentially (or serially) in successive physical positions from a first starting address, the latency time only appears for accessing the starting address. After the first data word of the serial data has been accessed within the latency time, the reading or writing operation of the sequential data successive to the first data word at the starting address can be executed with a memory speed which generally is much higher than the ‘speed’ to access the first data word and normally is the maximum speed supported by the memory. This operation is also called a first data accessing operation, i.e. accessing the first data word of a serial data. In general, the latency time occurs with every first data accessing operation. It is to be understood, that during this latency time no data is available and a running process requiring further data needs to wait for that further data.
FIG. 1
shows an example of a memory
10
comprising (amongst other data which is not indicated) a first serially stored data area
20
with data blocks
20
a
,
20
b
, and
20
c
, and a second serially stored data area
30
with data blocks
30
a
,
30
b
,
30
c
, and
30
d
, each stored in contiguous areas of the memory. The memory
10
is controlled by a processor
40
which accesses the memory
10
via a data connection
50
, which does not represent a fixed physical connection, but an access line from and to respective data blocks of the memory
10
, which might be embodied by any connecting means as known in the art. In the example of
FIG. 1
, the processor accesses data block
20
a
via the data connection
50
.
When the entire sequentially stored data area
20
is to be read, the latency time occurs only for accessing the (first) data block
20
a
, as the first data accessing operation. After accessing the data block
20
a
, the further data blocks
20
b
and
20
c
can be read with the memory speed. Accordingly, when the data area
30
is to be read, the latency time occurs only for accessing the data block
30
a
, as the first data accessing operation. After accessing the data block
30
a
, the further data blocks
30
b
,
30
c
, and
30
d
can be read with the memory speed.
In case that after accessing (e.g. for reading or writing) a first serial data, e.g. data area
20
or parts thereof, a second serial data is to be accessed, e.g. data area
30
or parts thereof, the latency time occurs first for accessing the first data word of the first serial data, e.g. data block
20
a
, and then again for accessing the first data word of the second serial data, e.g. data block
30
a
. This operation is also called a jump operation, i.e. jumping from one serial data to another serial data. In general, the latency time occurs with every jump operation.
In case that accessing a serial data, e.g. data area
20
or parts thereof, has to be repeated, the latency occurs between each accessing of the serial data. This operation is also called a repeat operation, i.e. repeating accessing a serial data. In general,

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