Memory interlace-checking method

Details Memory interlace-checking method Memory interlace-checking method

2007-03-27

2007-03-27

Lamarre, Guy J. (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

C714S720000

Reexamination Certificate

active

09886225

ABSTRACT:
The present invention relates to a memory interlace-checking method and, in particular, to a test method that can effectively detect the weakening of memory. This test method is different from the conventional continuous address testing style. It is an interlacing address test method that comprises a main step and a data checking step. The main step provides main data to perform command actions on local addresses in memory. This will weaken other portions in the memory that are not trigged by commands because of the electromagnetic interference (EMI) induced by memory operations. Afterwards, in the data checking step, the yet to be triggered portion will be checked in a complementary way in order to accurately detect weakened memory.

REFERENCES:
patent: 4513374 (1985-04-01), Hooks, Jr.
patent: 5297242 (1994-03-01), Miki
patent: 5748545 (1998-05-01), Lee et al.

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