Memory interface with write buffer and encoder

Details Memory interface with write buffer and encoder Memory interface with write buffer and encoder

2007-08-14

2007-08-14

Chase, Shelly (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

Reexamination Certificate

active

10960492

ABSTRACT:
A method and apparatus are provided for interfacing between a data source and a tightly-coupled memory. In the method and apparatus, a write data word and a write address are received from the data source and latched in a first clock cycle within a write buffer along a write data path, between the data source and the memory. The write data word is encoded according to an error detection code along the write data path. The write address and the write data word are applied to the memory from the write buffer. The write data word is accessible to the data source from the write data path or the memory beginning with a second clock cycle, which is a next subsequent clock cycle to the first clock cycle.

REFERENCES:
patent: 5226043 (1993-07-01), Pughe et al.
patent: 5453999 (1995-09-01), Michaelson et al.
patent: 5663969 (1997-09-01), Tsou

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