Electrical computers and digital processing systems: memory – Address formation – Combining two or more values to create address
Reexamination Certificate
2002-06-28
2004-09-28
Sparks, Donald (Department: 2187)
Electrical computers and digital processing systems: memory
Address formation
Combining two or more values to create address
C711S201000, C711S217000, C711S219000
Reexamination Certificate
active
06799261
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to the field of digital signal processing. More particularly, this invention relates to a memory interface that enables fractional addressing of data stored in the memory of a digital computer.
BACKGROUND OF THE INVENTION
Digital representations of images and signals are often obtained by discrete sampling in space, time or both space and time. For example, digital still pictures are sampled in space, digital audio signals are sampled in time and digital video signals are sampled in both time and space. When processing digital signals, the signals are often required at different sampling times or different positions. Examples include sample-rate conversion of audio and video signals, and rotation or translation of digital images. Estimates of the signals at intermediate sampling points can be obtained by interpolation, such as linear interpolation between adjacent points, or by simply using the nearest point for which a sample is available.
The computation of a linear interpolation involves finding the nearest (neighboring) points for which data values are available, calculating the distance to the neighboring points and calculating the interpolated value. This processing consumes a significant part of the resources of a digital processor.
Some digital processors are designed specifically for a particular kind of processing and the hardware, in the form of Application Specific Integrated Circuits (ASICs), is optimized for that processing. Examples include graphics accelerator chips. Graphics accelerators contain hardwired fractional address capabilities supporting a form a data interpolation of the ASICs intermediate or final results. None of these addressing schemes have been used in a programmable processor.
Digital Signal Processors (DSPs) offer flexible modes of address calculations, such as modulo and bit-reversed addressing, but do not provide fractional addressing.
REFERENCES:
patent: 6430671 (2002-08-01), Smith
Chiricescu Silviu
Essick, IV Raymond B.
Lucas Brian Jeffrey
May Philip E.
Moat Kent Donald
Chace Christian P.
Lamb James A.
Motorola Inc.
Sparks Donald
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