Electrical computers and digital processing systems: memory – Addressing combined with specific memory configuration or... – For multiple memory modules
Reexamination Certificate
1998-11-24
2003-07-29
Kim, Matthew (Department: 2186)
Electrical computers and digital processing systems: memory
Addressing combined with specific memory configuration or...
For multiple memory modules
C365S230030
Reexamination Certificate
active
06601130
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a memory interface unit for coupling a microprocessor to a memory external to the microprocessor, and to input/output devices of a memory-mapped type.
BACKGROUND OF THE INVENTION
In the U.S. Pat. No. 5,761,478, a programmable memory interface is disclosed for efficient transfer of different size data between a microprocessor of a given data and address bus width and memory banks of various data and address width, typically differing from the widths of the microprocessor's buses. In the examples given, the microprocessor, which has a 32 bit internal architecture, can execute programming code from 16 or 32 bit wide external memories, and can load and store 8, 16, and 32 bit data units into external memory and convert them into an internally equivalent 32 bit representation. Depending on the widths of the external memory banks, one external pin configures the memory width to 16 or 32 bit, and two sets of memory strobes and one I/O (input/output) strobe allow zero glue logic to two banks of memory and one bank of external peripherals. For 16 or 8 bit memories, one or two of four pins, otherwise all used as strobe-byte enable pins, are used as additional address pins. The behavior of the pins is manipulated according to the contents of certain registers. All memory banks are of the same directly addressable type. What is thus missing but needed is interfacing to mixed types of memory units, i.e, to generic memories such as ROM, SRAM, EPROM, Flash Memory, and memory-mapped I/O-devices on the one hand, and volatile memories such as DRAM which need refreshing on the other hand.
In the U.S. Pat. No. 4,349,870, a microcomputer with a programmable multi-function port is disclosed. One of a plurality of ports is user programmable by application of specific signals to mode selection pins. The programmable port comprises a number of lines which can be programmed as input or output lines to peripheral equipment, or, alternatively, can be programmed to serve as a bi-directional data bus to external memory.
In the U.S. Pat. No. 4,028,682, a circuit is disclosed for selecting the function of connecting contacts on circuit chips. Contacts can be selectively designated as either an input or an output contact.
In the U.S. Pat. No. 5,261,116, a programmable, expandable controller with flexible I/O is disclosed. An output buffer includes multiplexers which permit either a program counter or a control field to be multiplexed to output pins of a device. When the program counter is multiplexed to the output pins, the programmable controller can address external memory devices.
SUMMARY OF THE INVENTION
It is an object of the invention to provide a memory interface unit for flexibly coupling a microprocessor to a plurality of memory banks of different type, notably a mixture of generic type memory banks, such as ROM, EPROM, SRAM, Flash Memory, and memory-mapped I/O devices, and DRAMs.
It is another object of the invention to flexibly interface memory banks of different sizes, different bus width, different access times, different base addresses in a microprocessor memory space.
It is a further object of the invention to speed up program execution after booting up at a microprocessor reset.
It is still a further object to flexibly interface directly addressable memory-mapped input/output devices.
In accordance with the invention, a memory interface unit for coupling a microprocessor to a memory external to the microprocessor is provided, said memory being provided in the form of a plurality of memory banks, each of the memory banks being provided with address lines and data lines, at least a first memory bank of the plurality of memory banks being of a first type which is directly addressable, which first memory bank has a chip select input for selecting the first memory bank, and a second memory bank of the plurality of memory banks being of a second type, which is addressable by a row address and a column address, the row address being validated by a row address strobe at a row address strobe input of the second memory bank, and the column address being validated by a column address strobe at a column address strobe input of the second memory bank, said memory interface unit comprising:
unique strobes for each of the plurality of memory banks, which unique strobes are programmable in dependence of a type of memory bank to which a particular unique strobe relates, a first strobe of the unique strobes being programmed as a chip select signal which is inputted to the chip select input of the first memory bank, and a second strobe of the unique strobes being programmed as the row address strobe inputted to the row address strobe input of the second memory bank.
Preferably, the first memory bank is a non-volatile memory such as a ROM comprising executable code, located at a hard wired fixed address within the address space, and the second memory bank is volatile memory, preferable of DRAM type, the first and second memory bank being swapped after moving the executable code, and memory-mapped registers being defined in the second memory bank for at least configuring types, base addresses, sizes, bus widths, and access times of the memory banks.
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Kolb William W.
Lee Frank S.
Silvkoff William J.
Anderson Matthew D.
Kim Matthew
Koninklijke Philips Electronics , N.V.
LePennec Gwenaelle
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