Memory, interface system and method for mapping logical...

Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C711S202000, C711S206000, C714S006130

Reexamination Certificate

active

06427186

ABSTRACT:

TECHNICAL FIELD
The present invention relates to defect management in flash memory devices and, in particular, to an interface controller to such a memory that includes circuitry to reliably track, and prohibit access to, defective sectors.
BACKGROUND
The use of electrically erasable memory is well-known in the art. For example, standards for “flash” memory and circuits for controlling access to the flash memory have been defined by the Personal Computer Memory Card International Association (PCMCIA) and Compact Flash Association (CFA). PCMCIA-compliant cards have been used with portable computers as an adjunct to (or instead of) a hard drive and, more recently, for such devices as digital cameras.
Where an electrically erasable memory can be programmed in one size “chunk”, but can only be erased in another (larger) size “chunk”, complexity is introduced into the programming operation. For example, with one particular flash memory media, the media can be programmed sector by sector, but can only be erased in segments (which are multiple sectors). Furthermore, where there are manufacturing defects in the memory, which is quite common, this conventionally requires a large amount of overhead to efficiently avoid the defects without also having to disregard a large portion of non-defective memory.
SUMMARY
An interface system interfaces a host processor to an electrically-erasable memory in a memory space, such as a flash media. The memory space defines a plurality of segments. A media interface circuit regulates access by the host processor to the electrically-erasable memory in the memory space. The host processor requests access to the memory based on a logical block number.
The interface system includes:
means for using the logical block number to determine from a master index table a physical sector number of a table of physical sector numbers corresponding to the logical block number; and
means for using the logical block number to determine from the table of physical sector numbers the physical sector number on the media corresponding to the logical block number.
With such a system, the memory can be efficiently remapped to address both manufacturing defects and programming considerations.


REFERENCES:
patent: 5432748 (1995-07-01), Hsu et al.
patent: 5526335 (1996-06-01), Tamegai
patent: 5630093 (1997-05-01), Holzhammer et al.
patent: 5742934 (1998-04-01), Shinohara
patent: 5875477 (1999-02-01), Hasbun et al.
patent: 5905993 (1999-05-01), Shinohara
patent: 5933852 (1999-08-01), Jeddeloh
patent: 5946714 (1999-08-01), Miyauchi
patent: 6016275 (2000-01-01), Han
patent: 6069827 (2000-05-01), Sinclair
patent: 6081878 (2000-06-01), Estakhri et al.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Memory, interface system and method for mapping logical... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Memory, interface system and method for mapping logical..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory, interface system and method for mapping logical... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-2887885

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.