Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area
Reexamination Certificate
1998-05-22
2001-05-29
Yoo, Do Hyun (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Shared memory area
C711S147000, C711S169000, C382S166000
Reexamination Certificate
active
06240492
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This invention relates to co-pending, commonly assigned U.S. patent application Ser. No. 09/047,139, filed Mar. 24, 1998, now U.S. Pat. No. 6,038,630, entitled “Shared Access Control Device For Integrated System With Multiple Functional Units Accessing External Structures Over Multiple Data Buses,” the entirety of which is hereby incorporated herein by reference.
TECHNICAL FIELD
Generally stated, this invention relates to data request handling and processing within an integrated system, and more particularly, to a memory interface for a functional unit thereof which allows the functional unit simultaneous access to dedicated memory and shared memory, and which provides speculative generation of lookahead fetch requests for enhanced processing using the dedicated memory.
BACKGROUND OF THE INVENTION
Multiple functions are today commonly being integrated onto a single system chip. When initially defining architecture for integration of multiple discrete components onto a single chip, access to external devices can be a critical issue. For example, an MPEG video decoder system often employs external memory for various data areas, or buffers such as frame buffers. This external memory is typically implemented using either DRAM or SDRAM technology. In the decoder system, a video decode unit requires immediate access to external memory when needed to prevent starving the video display or on-screen graphics. If the video decoder's request for data is delayed, the picture could be corrupted. Likewise, an on-chip processor, if held from accessing external memory when needed could experience significant performance degradation.
Two approaches are typical in the art for accessing off-chip devices. In a first approach, each on-chip functional unit is given access to the needed external device(s) through a data bus dedicated to that particular unit. Although locally efficient for accessing the external device, globally within the integrated system this approach can be less than optimal. For example, although each function will have complete access to its own external memory area, there is no shared access between functions of the integrated system. Thus, transferring data from one memory area to another memory area of the system is often needed. This obviously increases data transfers and can thus degrade performance of the overall system, i.e., compared with a shared memory system. Also, when implementing strictly dedicated memory, the total memory size required may result in a non-standard memory increment that will have a cost premium attached. For instance, today's standard increments are in multiples of 8 megabytes. Therefore, to implement dedicated memory requiring 9 megabytes using standard increments would require two 8 Mbyte dedicated memories, totalling 16 megabytes.
Another approach is to employ a shared or common bus within the integrated system which allows one or more functional units of the system to communicate with external memory through a single port. Although allowing the sharing of memory, the difficulty with this approach arises when many functions are integrated onto a single chip, with each function requiring a certain amount of bandwidth for accessing data in shared memory. In implementation, the bandwidth of the single data bus needs to be sufficient to accommodate all functional units communicating through the bus. This bandwidth requirement can become prohibitive.
For example, in a video decode system, a video decode unit may require 100 Mbytes/sec of bandwidth, while a transport unit may require up to 5 Mbytes/sec of bandwidth, a processor unit up to 50 Mbytes/sec and an audio decoder up to 5 Mbytes/sec. Thus, with a single data bus serving these functional units, 160 Mbytes/sec of bandwidth would be needed. Further, in this example, each functional unit may be required to possess a large amount of internal buffering to span the time gap between memory accesses resulting from having multiple bandwidths sharing communications through the single bus. These bandwidth and buffer requirements associated with a shared bus implementation make a strictly shared bus/port implementation less than ideal for today's ever more integrated technologies. However, the use of shared memory does advantageously allow multiple functions to move data into and out of a common space efficiently, and since memory is shared with other applications, larger memory increments or granularity are possible, thereby allowing the use of standard or commodity components.
Therefore, there exists a need in the art for a memory interface for a functional unit of an integrated system which allows the functional unit to simultaneously access both dedicated memory and shared memory through multiple ports while avoiding the performance degradation and increased costs inherent in a solely dedicated approach to external memory. In one aspect, the present invention is directed to meeting this need.
DISCLOSURE OF THE INVENTION
Briefly described, the present invention comprises in one aspect a memory interface for a functional unit of an integrated system. The memory interface includes multiple memory ports, at least one memory port being coupled to dedicated memory and at least one memory port being coupled to shared memory. The dedicated memory comprises private memory for the functional unit and the shared memory comprises common memory coupled to the functional unit and at least one additional functional unit of the integrated system. The memory interface further includes a receiver for receiving memory fetch requests from at least one requesting unit within the functional unit and a controller for controlling forwarding of each memory fetch request to either the dedicated memory or the shared memory.
In another aspect, the invention encompasses an integrated system which is coupled to dedicated memory and shared memory. The integrated system includes a shared system data bus and multiple functional units coupled to the shared system data bus for sending requests thereon to access the shared memory. One functional unit of the multiple functional units includes a memory interface. The memory interface has multiple memory ports, with one memory port being coupled to the shared system data bus, and one memory port coupled to the dedicated memory for sending requests thereto. The dedicated memory comprises private memory for the one functional unit containing the memory interface.
In a further aspect, the invention includes a memory interface for a functional unit of an integrated circuit. This memory interface includes at least one memory port coupled to dedicated memory, which comprises private memory for the functional unit. A receiver is provided for receiving memory fetch requests from at least one requesting unit within the functional unit. Additionally, a lookahead request generator is provided for generating lookahead fetch requests within the memory interface using information from the received memory fetch request, and known memory access patterns. A controller is provided for forwarding each memory fetch request and each lookahead fetch request to the dedicated memory. The controller forwards the fetch requests so as to optimize bandwidth on a channel coupling the at least one memory port and the dedicated memory.
In a yet further aspect, the invention comprises an integrated system coupled to dedicated memory. The integrated system includes a functional unit connected to the dedicated memory across a memory interface. The memory interface includes at least one memory port coupled to the dedicated memory so that the dedicated memory comprises private memory to the functional unit. The memory interface further includes a receiver and a lookahead request generator. The receiver receives memory fetch requests from at least one requesting unit of the functional unit, and the lookahead request generator generates lookahead fetch requests using information from the received memory fetch request and using known memory access patterns of the functiona
Foster Eric M.
Herndon Steven B.
Ngai Chuck H.
Heslin & Rothenberg, P.C.
International Business Machines - Corporation
Moazzami Nasser
Steinberg William H.
Yoo Do Hyun
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