Memory interface controller

Details Memory interface controller Memory interface controller

1998-08-28

2001-05-15

Kim, Matthew (Department: 2186)

Electrical computers and digital processing systems: memory

Addressing combined with specific memory configuration or...

Addressing extended or expanded memory

C711S156000

Reexamination Certificate

active

06233646

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a memory interface controller for a data transmission system, and in particular, to an improved memory interface controller which is capable of randomly accessing a memory using an associative memory and processing data variable-length using an extended memory.
2. Description of the Conventional Art
In the data transmission system, when data are transmitted by the data frame unit of a data link level, the data to be transmitted are sequentially stored in a buffer and then transmitted. If a data frame is missed or an error occurs in the data frame, the data are retransmitted using a known buffer memory by a software-based processing method.
The above-described software-based processing methods using a known buffer memory are disclosed in the following patents and articles.
First, a U.S. Pat. No. 5,404,483 filed on Jun. 29, 1990 by the inventors “Rebecca L. Stamm et al. and entitled “Processor and method for delaying the processing of cache coherency transactions during outstanding cache fills” is disclosed.
In the patent '483, since the data are distributed to multi processor computers, it is needed to check where the data are distributed in the computer system. Namely, the patent '483 is directed to storing the address of the designated memory, storing the same into a content addressable memory, accessing the content addressable memory and then searching the address of the memory in which the data are stored.
There is another patent entitled “Address translation circuit used for paging, segmentation in power PC architecture” having a U.S. Pat. No. 0,222,779 and filed on Apr. 4, 1994.
The above-described patent '779 is directed to configuring an address converter using a content addressable memory for implementing a data paging and segmentation when configuring a data processing block in a processor chip.
An article entitled “Searching databases for words: CAM(CContent Addressable Memory)” is disclosed by NASA on the web server.
The above-described article is obtained based on various web servers with respect to the content addressable memory. In this article, it is known that the CAM is applicable to a neutral network and pattern recognition.
There is another article of “1995 Project summaries: Content addressable memory project” by DARPA on the web server.
The above-described article is made based on “a content addressable memory project” by Rutgers university.
In this project, the CAM is employed for an application such as a data base which is not supported by a conventional architecture. The project is directed to a new architecture for substituting a conventional memory, not the processor in the computer system.
The thusly manufactured memory has a good performance for processing a large capacity data.
There is another article entitled “CAM5 specification” by CNU and NASA.
This article is made based on a CAM standard of a 256 work×32-bit and a combined project of Christopher Newport University (CNU), NASA and CEBAT National institute. In the article, a 3-layer CMOS having 68 pins and 0.8 microns is disclosed.
In addition, several articles are searched on the internet using Altavista, which is one of the strongest web browsers. As a result of the search, about 400 items are matched. Among these articles, the following articles will be explained.
In an article entitled “RNS 1250 series VME bus FDDI adaptor” by RNS, a FDDI adaptor card using a content addressable memory, by the RNS is disclosed. This card is directed to detecting a group address using a CAM of 512×48-bit.
In another article entitled “Circuit arrangement for line units of an ATM switching equipment” by MicroPatent on the web server, a CAM used for processing a path information of a virtual connection in an ATM switching is disclosed.
In another article entitled “GIGA switch system: A high performance packet-switching platform” by DEC on the web server”, the GIGA switch which is capable of processing a polynomial of 47 degrees using a CAM in a crossbar switch fabric of 36 point 100 Mbps is disclosed.
In another article entitled “Memory hierarchy” by Rutgers university on the web server, a characteristic and application method of a content addressable memory which is made based on several memory structures is disclosed. Here, the CAM is called as an associate memory and is capable of reading a corresponding data when a RAM applies an address. The CAM is capable of obtaining an address stored in a corresponding data when a data is applied.
In another article entitled “The 80196KC microcontroller” by Intel on the web server, the chip is a 16-bit data and 16-bit address chip which is capable of processing an event of a timer for outputting data at high speed.
In another article entitled “Associate memory” by J. P. Hayes in A McGrow-Hill, a data sheet of a content addressable memory is disclosed.
However, in the above-described patents, in order to easily obtain an address information of the memory, the address information of the content addressable memory is stored, and a data value to be searched is applied using a content addressable memory as a basic function. In the conventional art, a function capable of processing a data block having a variable length as an identifier is not disclosed.
In accordance with a research trend and application range of a CAM field of the above-described articles, the CAM is used for a routing table matching in a pattern matching operation and communication for a neural network and an intelligent system and a polynomial computation of a data for a data communication. In the above-described articles, the feature of the content addressable memory project is not disclosed except in the content addressable memory project implemented by Rutgers university. The data processing by Rutgers university is basically directed to the CAM. Therefore, it is known that the subject matters of the present invention are not disclosed in the above-described patents and articles.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a memory interface controller which overcomes the aforementioned problems encountered in the conventional art.
It is another object of the present invention to provide a memory interface controller which is capable of randomly accessing a memory using an associative memory and variably processing data using an extended memory.
In order to achieve the above objects, there is provided a mermory interface controller which includes a control logic unit for selectively outputting a 9-bit priority match address (
8
:
0
), a 9-bit externalmemory empty address, a 9-bit memory empty address, a 9-bit extended memory empty address, a read enable signal RD, a write enable signal WR, a Daisy-chain enable signal and an enable signal in accordance with a 16-bit sequence number SN
16
, a 2-bit instruction signal, a 8-bit data signal, a 9-bit priority match address, a 9-bit external memory empty address, and a 9-bit external extended memory empty address for thereby controlling a read/write operation of the data; a comparand register for storing a sequence number SN from the control logic unit; an associative memory for comparing the SN stored in the comparand register with a previously stored SN and outputting a match address in accordance with a result of the comparison; a priority address encoder for outputting a priority match address from the associative memory to the control logic unit; an external memory controller enabled in accordance with an enable signal from the control logic unit for outputting an empty address of the associative memory; an external tended memory controller for outputting a priority empty address from each block of the extended RAM to the control logic unit in accordance with an enable signal from the control logic unit; and an extended memory address and control signal generator for generating an address and a control signal (enable/read/write) and outputting to the RAM and the extended RAM in accordance with a r

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