Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis
Reexamination Certificate
2006-07-17
2010-02-16
Bae, Ji H (Department: 2115)
Electrical computers and digital processing systems: support
Clock, pulse, or timing signal generation or analysis
C713S400000, C713S401000, C713S503000, C711S100000
Reexamination Certificate
active
07664978
ABSTRACT:
Integrated circuits such as programmable logic device integrated circuits with memory interface circuitry are provided. The memory interface circuitry measures the timing characteristics of an associated memory during a series of dummy read operations. A multiplexer and phase detector are used to measure phase shifts of memory group clock signals compared to a system clock signal. The memory interface circuitry uses these measurements to adjust a delay-locked-loop circuit. The delay-locked-loop circuit produces a capture clock that is used to read data from the memory.
REFERENCES:
patent: 6509762 (2003-01-01), Moss et al.
patent: 6570944 (2003-05-01), Best et al.
patent: 6600681 (2003-07-01), Korger et al.
patent: 6664838 (2003-12-01), Talledo
patent: 6930932 (2005-08-01), Rentschler
patent: 6985096 (2006-01-01), Sasaki et al.
patent: 7003423 (2006-02-01), Kabani et al.
patent: 7075365 (2006-07-01), Starr et al.
patent: 7457174 (2008-11-01), Braun et al.
patent: 2001/0033188 (2001-10-01), Aung et al.
patent: 2004/0076055 (2004-04-01), Harrison
patent: 2005/0047192 (2005-03-01), Matsui et al.
patent: 2005/0104638 (2005-05-01), Saeki
patent: 2005/0278131 (2005-12-01), Rifani
“Stratix II GX Transceiver Block Overview” Stratix ll GX Device Handbook, vol. 2, pp. 1-1 to 1-8, Altera Corporation, Feb. 2006.
“Stratix II BX Physical Coding Sub-Layer”, pp. 1-3 printed from www.altera.com on Mar. 21, 2006, Altera Corporation.
“Stratix II GX Transceiver FPGAs Physical Medium Attachment Layer”, pp. 1 and 2, printed from www.altera.com on Mar. 21, 2006, Altera Corporation.
“Source Synchronous Signaling in Stratix II Devices”, pp. 1 and 2, printed from www.altera.com on Mar. 21, 2006, Altera Corporation.
“Interfacing DDR & DDR@ SDRAM with Cyclone II Devices”, Application Note AN-361-1.3 of Altera Corporation, pp. 1-42 (2006).
Burney Ali
Charagulla Sanjay K.
Altera Corporation
Bae Ji H
Ru Nancy Y.
Treyz G. Victor
Treyz Law Group
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