Memory interface circuit having plurality of prefetch...

Details Memory interface circuit having plurality of prefetch... Memory interface circuit having plurality of prefetch...

2006-07-04

2006-07-04

Kim, Matthew (Department: 2186)

Electrical computers and digital processing systems: memory

Address formation

Generating prefetch, look-ahead, jump, or predictive address

C711S217000, C711S119000, C711S125000

Reexamination Certificate

active

07073045

ABSTRACT:
Each prefetch buffer has a tag register for storing a branch address and a data register for storing instruction data. Each of the prefetch buffers is assigned to either a first prefetch buffer rewritable during a normal operation period and a second prefetch buffer to be disabled for rewrite during the normal operation period. The second prefetch buffer can thus be prevented from being rewritten even if a central processor outputs branch addresses frequently. This realizes an improvement in the instruction fetch efficiency of the central processor and an improvement in the entire system performance. The fetch efficiency can be improved particularly in such systems that branch addresses occur frequently and some of them occur repeatedly.

REFERENCES:
patent: 5680564 (1997-10-01), Divivier et al.
patent: 2004/0260908 (2004-12-01), Malik et al.
patent: 62-259158 (1987-11-01), None
patent: 6-028258 (1994-02-01), None
patent: 2000-347931 (2000-12-01), None

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