Memory interface circuit

Details Memory interface circuit Memory interface circuit

2002-01-14

2003-01-21

Kim, Matthew (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

C711S150000, C711S151000, C365S222000, C365S205000, C365S189080, C710S040000, C710S244000, C710S305000

Reexamination Certificate

active

06510489

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a memory interface circuit comprising a function for refreshing memory. The present invention can be applied to a memory interface circuit, which is used, for example, in an ordinary DRAM (Dynamic Random Access Memory), and a synchronous DRAM.
2. Description of Related Art
As is commonly known, a DRAM stores binary data in accordance with whether or not a charge is stored on a capacitor in each memory cell. For this reason, an operation, which replenishes the charge to each memory cell capacitor, is necessary to prevent a memory value from being destroyed by capacitor leakage current. This operation is called “refresh.”
In a DRAM, refresh must be performed cyclically to ensure the prevention of memory data destruction. Therefore, in an ordinary DRAM, the execution of a refresh operation takes priority over a read/write operation. That is, a DRAM will make a read/write access wait, and accept a refresh access first.
However, if read/write access is made to wait every refresh cycle, the time required for a DRAM read operation and write operation will substantially increase. For this reason, for a highspeed system, there are cases in which the performance of the entire system deteriorates because read/write operations are slow. Further, depending on the system, there are also cases in which malfunctions occur because of a slow response to a read/write request.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a memory interface circuit, which is capable of executing at high speed other processes in memory, while ensuring the prevention of memory data destruction.
(1) In accordance with a first standpoint of the present invention, a memory interface circuit comprising memory bus arbitrating means, which is inputted with a plurality of types of refresh request signals, and 1 type, or a plurality of types of other processing request signals, and which selects from among the simultaneously-inputted request signals the one with the highest priority; memory controlling means for controlling memory on the basis of a request signal selected by memory bus arbitrating means; counting means for counting timing for refreshing memory; and a plurality of types of monitoring means for outputting refresh request signals with mutually differing priorities at mutually differing timing in accordance with a counting value of counting means.
(2) In accordance with a second standpoint of the present invention, a memory interface circuit comprising memory bus arbitrating means, which is inputted with a refresh request signal, and other processing request signals, and selects from among the simultaneously-inputted request signals the one with the highest priority; memory controlling means for controlling memory on the basis of a request signal selected by memory bus arbitrating means, and output a termination signal when a prescribed processing among other processing ends; counting means for counting timing for refreshing memory; monitoring means for outputting a refresh request signal in accordance with a counting value of counting means; and gate means for supplying a refresh request signal to memory bus arbitrating means when a termination signal is outputted.
(3) In accordance with a third standpoint of the present invention, a memory interface circuit comprising memory bus arbitrating means, which is inputted with a refresh request signal, and other processing request signals, and selects from among the simultaneously-inputted request signals the one with the highest priority; memory controlling means for controlling memory on the basis of a request signal selected by memory bus arbitrating means; counting means for counting timing for refreshing memory; and monitoring means for outputting a refresh request signal on the basis of a result of comparing a count value of this counting means against a comparison value stored in overwrite-capable memory.


REFERENCES:
patent: 4106108 (1978-08-01), Cislaghi et al.
patent: 4535330 (1985-08-01), Carey et al.
patent: 4600992 (1986-07-01), Boudreau et al.
patent: 4829467 (1989-05-01), Ogata
patent: 4849936 (1989-07-01), Mizutani
patent: 4956820 (1990-09-01), Hashimoto
patent: 5216635 (1993-06-01), Kass et al.
patent: 5418920 (1995-05-01), Kuddes
patent: 5479372 (1995-12-01), Sato et al.
patent: 5524235 (1996-06-01), Larson et al.
patent: 5557578 (1996-09-01), Kelly
patent: 5583823 (1996-12-01), Park
patent: 5706482 (1998-01-01), Matsushima et al.
patent: 06020468 (1994-01-01), None
patent: 09106674 (1997-04-01), None

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