Memory interface

Details Memory interface Memory interface

2007-12-31

2009-08-18

Yoha, Connie C (Department: 2827)

Static information storage and retrieval

Read/write circuit

Signals

C365S193000, C365S226000, C365S233100

Reexamination Certificate

active

07577048

ABSTRACT:
A double data rate memory interface circuit for transferring data between an interfacing device and double data rate memory device. The interface circuit comprises a data input for receiving a data signal from a first of those devices, and a strobe input for receiving a strobe signal from that first device. The interface circuit also comprises delay circuitry for supplying the data and strobe signals to the other device with a timing offset introduced therebetween. The delay circuitry comprises a software programmable storage medium and a digitally controllable delay element coupled to the storage medium, the delay element being arranged to control the timing offset in dependence on a delay setting programmed into that storage medium.

REFERENCES:
patent: 6292412 (2001-09-01), Kato et al.
patent: 6850458 (2005-02-01), Li
patent: 7274605 (2007-09-01), Stubbs

Affiliated with

Also associated with

Rating

Memory interface does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Memory interface, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory interface will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4075686