Memory integrated circuit with shared read/write line

Details Memory integrated circuit with shared read/write line Memory integrated circuit with shared read/write line

1998-07-14

1999-10-05

Nelms, David

Static information storage and retrieval

Read/write circuit

Simultaneous operations

36518905, 36523008, 365 63, G11C 1604

Patent

active

059634820

ABSTRACT:
A memory device is provided with N>1 memory arrays. Each of the memory arrays comprises a plurality of memory cells arranged into rows and columns. N I/O lines are provided that can be simultaneously activated during a prefetch cycle. Each of the I/O lines is connected to the memory cells of a different one of the N memory arrays for transferring data signals to and from specific addressed ones of the memory cells of the respective memory array. N latches are also provided wherein each of the latches is connected to a different one of the I/O lines. Furthermore, a read/write line is connected to each of the latches and extends along an edge of each memory array. During a prefetch cycle, each of the N I/O lines simultaneously transfers a data signal thereon. Each of the N latches receives a different phase clock signal for synchronizing a transfer of N data signals, including one data signal of each of the latches. The data signals are transferred between the latches and the read/write line so that each data signal is transferred during a respective different n.sup.th interval of a transfer cycle, where 1.ltoreq.n.ltoreq.N. As such, N data signals, including one data signal originating at, or destined to, each of the N memory arrays, are transferred sequentially via the read/write line during the prefetch cycle.

REFERENCES:
patent: 5088062 (1992-02-01), Shikata
patent: 5367494 (1994-11-01), Shebanow et al.
patent: 5412613 (1995-05-01), Galbi et al.
patent: 5640351 (1997-06-01), Yabe et al.

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