Memory integrated circuit with redundancy and improved addressin

Details Memory integrated circuit with redundancy and improved addressin Memory integrated circuit with redundancy and improved addressin

1991-08-08

1993-09-21

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Bad bit

36523001, 365201, G11C 1300

Patent

active

052474810

ABSTRACT:
Integrated circuit memories provided with redundancy means enable the lines or columns of defective cells to be repaired. In order to avoid incompatibility between the addressing modifications due to a "grouped test" and those due to placing a redundant column or line into service, means are provided for the addressing, in grouped test mode, not only of several selected columns or lines of the memory but also of a redundant column or line that may have been put into service to replace a defective one of the selected columns or lines.

REFERENCES:
patent: 4907203 (1990-03-01), Wada et al.
patent: 4939694 (1990-07-01), Eaton et al.
patent: 5007026 (1991-04-01), Gaultier et al.
Altnether et al, "Testing Redundant Memories", IEEE Electro, vol. 7, pp. 26/3(1-6), New York (May 1982).
"Fast Write Scheme for Memory Test Patterns", Research Disclosure, No. 299, Disclosure No. 29929, p. 173, New York, New York (Mar. 1989).

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