Memory integrated circuit with improved reliability

Details Memory integrated circuit with improved reliability Memory integrated circuit with improved reliability

2002-03-21

2003-06-24

Nguyen, Tan T. (Department: 2818)

Static information storage and retrieval

Systems using particular element

Ferroelectric

C365S149000

Reexamination Certificate

active

06584009

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to ferroelectric memory integrated circuits (ICs). More particularly, the invention relates to improving the reliability of ferroelectric memory ICs configured in a chained architecture.
BACKGROUND OF THE INVENTION
Ferroelectric metal oxide ceramic materials such as lead zirconate titanate (PZT) have been investigated for use as ferroelectric capacitors of semiconductor memory devices. Other ferroelectric materials including, for example, stronthium bismuth tantalate (SBT) or bismuth lanthanum titanate (BLT) can also be used. The ferroelectric material is located between two electrodes to form a ferroelectric capacitor for storage of information. Ferroelectric capacitor uses the hysteresis polarization characteristic of the ferroelectric material for storing information. The logic value stored in the memory cell depends on the polarization of the ferroelectric capacitor. To change the polarization of the capacitor, a voltage which is greater than the switching voltage (coercive voltage) needs to be applied across its electrodes. The polarization of the capacitor depends on the polarity of the voltage applied. An advantage of the ferroelectric capacitor is that it retains its polarization state after power is removed, resulting in a non-volatile memory cell.
FIG. 1
shows a plurality of memory cells
105
. The memory cells each comprising a transistor
130
coupled to a ferroelectric capacitor
140
in parallel. The memory cells are coupled in series to form a chain
103
. Chained memory architectures are described in, for example, Takashima et al., “High Density Chain ferroelectric random access Memory (chain FRAM)”, IEEE Jrnl. of Solid State Circuits, vol.33, pp.787-792, May 1998, which is herein incorporated by reference for all purposes. One end of a chain is coupled to a bitline
160
via a selection transistor
108
while the other end is coupled to a plateline
170
. The gates of the transistors are coupled to respective wordlines
150
. The bitline is coupled to a sense amplifier circuit to facilitate memory accesses (e.g., reads and writes).
FIG. 2
shows a timing diagram of a read operation for accessing a memory cell of the chain. Prior to T
1
, the memory cells are in standby mode. During standby mode, the BS signal is at a logic 0 (;ground or Vss), rendering the selection transistor non-conductive to decouple the chain from the bitline. The wordlines coupled to the gates of the memory cells are at a boosted high voltage level (Vpp), shorting the capacitors. The boosted voltage is greater than the internal voltage (Vint) of the IC. In particular, Vpp has to be sufficiently high to ensure sufficient overdriving during read or write operations. For example, Vpp is about 3.8 V while Vint is about 2.5 V.
At about T
1
, the wordline associated with the selected cell is driven to a logic 0 while the wordlines of the non-selected cells remain at Vpp. At about T
2
, the BS signal is driven to Vpp to couple the chain to the bitline. A pulse (Vpl which for example is about 2.5V) is then provided on the plateline until about T
3
. The pulse creates an electric field across the capacitor of the selected cell. A signal corresponding to the information stored in capacitor is then placed on the bitline and sensed by a sense amplifier. After the access is completed, the chain is decoupled from the bitline by driving BS to a logic 0 at T
4
. The selected wordline is then driven back to Vpp at T
5
, thus returning to the standby mode.
As shown by the timing diagram, the wordlines are maintained at Vpp during standby mode. Even during a memory access, only the wordline associated with the selected cell is driven to logic 0. Applying a boosted voltage to the gates almost constantly can adversely affect the reliability of the gate oxide, reducing service lifetime of the memory device.
From the foregoing discussion, it is desirable to provide a chained architecture with improved reliability.
SUMMARY OF THE INVENTION
The invention relates to improving reliability of memory ICs with chained architectures. In one embodiment, a multi-level voltage scheme is used to drive the wordlines. During standby mode, the wordlines are maintained at a first or reduced logic 1 voltage level. When a memory access is to be performed, the non-selected wordlines are driven to a boosted voltage level while the selected wordline is driven to Vss or logic 0. The boosted voltage level is greater than the first voltage level to ensure sufficient overdriving of the transistors of the memory cell. By providing a multi-level voltage scheme to operate the wordlines, the gates of the transistors are exposed to the high voltage only when necessary. This reduces stress on the gate oxide, thus improving reliability.


REFERENCES:
patent: 6094370 (2000-07-01), Takashima
patent: 6493251 (2002-12-01), Hoya et al.
patent: 6507510 (2003-01-01), Takashima

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