Electrical computers and digital processing systems: memory – Storage accessing and control – Memory configuring
Reexamination Certificate
1998-04-27
2001-07-17
Ellis, Kevin L. (Department: 2185)
Electrical computers and digital processing systems: memory
Storage accessing and control
Memory configuring
C709S247000
Reexamination Certificate
active
06263413
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a memory integrated circuit with a data compression/decompression function, and a main memory system and a graphics memory system applying such memory integrated circuit. In particular, the present invention relates to a large-capacity semiconductor memory LSI (large scale integrated circuit) which could be represented by a dynamic random access memory (DRAM), and utilized in constructing a main memory system and graphics memory system within a computer system.
DESCRIPTION OF THE RELATED ART
With respect to a semiconductor memory LSI, it is regarded as typical that the larger the memory capacity is, the larger the data bandwidth should become in accessing to the memory contents. This is due to the fact that this large-capacity semiconductor memory LSI is normally applied to a high-performance computer system which requires a considerably large data bandwidth.
Therefore, in order to achieve a more convenient memory LSI for the computer system, it is extremely important that the memory capacity of the memory LSI and the data bandwidth are balanced. Accordingly, with respect to the DRAM being the memory LSI with the largest capacity, technical development has been sought with some enthusiasm in order to obtain an improved data bandwidth.
The most typical method for improving the data bandwidth of the memory LSI is a method of rising the operating frequency of the external interface. Currently, the highest bandwidth possible for the memory LSI is achieved by the Rambus technique, as the highest bandwidth is 600 Mbits/s per signal line with the application of both edges of a clock with 300 MHz. “Rambus” is the official trademark of Rambus Inc., US, and the mentioned Rambus technique is a technique proposed by Rambus Inc..
Technically, raising the operating frequency of the external interface to a higher value than the one just mentioned could be extremely difficult. One of the problems is a simultaneous operation of the external input/output signal terminals. When a large number of signal terminals are to operate simultaneously in high-speed, the chip will have to deal with larger consumption of power, and a large switching noise will be induced, causing a poor performance of the memory LSI.
Time discrepancies, i.e. skew, among signal lines could be a serious problem, too. For it is difficult to completely equalize the electrical parameters of the signal lines on the board, time discrepancies caused by inconsistency among electrical parameters must become an obstacle with respect to a high-speed operation of a GHz-level.
Generally, a main memory system of a computer would have a structure in which a plurality of DRAMs are connected to a memory bus. On the memory bus, however, disarray of signal waveforms inevitably occurs due to impedance mismatching etc., which could be another obstacle to the high-speed operation.
Consequently, it has become difficult to improve the data bandwidth by simply rising the operating frequency of the external interface according to the conventional technique. Moreover, as the memory LSI applying a high-speed interface and the memory system employing the memory LSIs are generally expensive, a proposal for achieving a high-bandwidth memory system with less memory LSIs by reducing the amount of data to be transferred with the application of a data compression method has come to a focus.
Conventionally, this type of technique has been used for transferring graphics data. This is based on the fact that graphics data is proved to be highly suitable for data compression, i.e. it has a high compression ratio because of its redundancy and consistency. Besides, in transferring graphics data, a large data bandwidth is required in both the graphics memory system and the main memory system.
The above technique is being proposed in “New DRAM Technologies—A Comprehensive Analysis of the New Architectures (Second Edition)” (Steven A. Przybylski, MicroDesign Resources, 1996, pp. 124-127).
The technique proposed in the above-mentioned paper will be described with reference to
FIG. 1. A
frame buffer
8
shown in the figure constituted by the memory LSI is a memory system used particularly for screen-write in the graphics memory system.
In this memory system, the frame buffer
8
is provided with an uncompressed write-data area
81
for the uncompressed write-data, and a compressed write-data area
82
for the compressed write-data. Each of those areas is arranged as a set of blocks in a particular region of the screen.
When a write transaction is to be taken with respect to a certain block, first, a graphics controller
9
is to check the compressed write-data corresponding to that particular block, i.e. the data in the compressed write-data area
82
. When the compressed write-data is being marked as valid, the graphics controller
9
is to take the write transaction using the compressed write-data. On the other hand, when the compressed write-data is being marked as invalid, it will take the write transaction using the uncompressed write-data corresponding to the block, i.e. the data in the uncompressed write-data area
81
.
In the latter case, when the graphics controller
9
identifies that the compressed write-data is invalid, the graphics controller
9
will compress the uncompressed write-data read out from the uncompressed write-data area
81
so as to write it on a corresponding block in the compressed write-data area
82
. In this occasion, the compressed write-data written on the compressed write-data area
82
will be marked as valid.
When the graphics controller
9
is to rewrite the write-data, it will rewrite the data in the uncompressed write-data area
81
. When this happens, the compressed data in the block of the compressed write-data area
82
which corresponds to the one being rewritten will be marked as invalid. This means that only the compressed version of the newly rewritten data will be marked as invalid.
With the application of the above process, it becomes possible to reduce the amount of data transmission needed for screen-write. It has not been mentioned in particular about the method of compression with respect to graphics data. However, this could be dealt with a provision of a graphics controller which performs data compression with software or hardware. Such compression method for data having redundancy and consistency is mentioned in “A technique for High-Performance Data Compression” (Terry A. Welch, IEEE Computer, June 1984, pp. 8-19). The extent of reduction on the amount of data transmission which could be obtained by this particular technique usually depends on a kind of compression method taken, and on the type of data used. Yet, it is generally expected that data transmission can be reduced to approximately a half to {fraction (1/10)}.
According to the above-mentioned memory system of the conventional type using the data compression technique, it is possible to dramatically reduce the amount of data transmission with respect to data for screen-write, as compared with the case of not performing data compression. However, such a technique can induce certain problems which will be described below.
Some transactions requiring transferring of graphics data includes screen-write, reading of image data, screen-rewrite etc.. Especially when it comes to 3D graphics transactions, a larger amount of bandwidth as compared with the screen-write process is required for reading texture data, accessing to a Z-buffer, writing polygons (i.e. screen-rewrite) etc.. Texture data as a term is a data of patters for use as backgrounds and in covering stereoscopic surfaces, with respect to a graphics software. The Z-buffer is a buffer for holding data relating to the direction of Z-axis in a 3D graphics transaction.
For example, referring to a technique as mentioned in “AGP Speeds 3D Graphics” (Yong Yao, Microprocessor Report Vol. 10, No. 8, Jun. 17, 1996), bandwidth requirements for a screen with 1024×768 pixels will be as follows: 150 Mbytes/s for screen-write, 200 Mbytes/s for scree
Aimoto Yoshiharu
Motomura Masato
Yabe Yoshikazu
Ellis Kevin L.
NEC Corporation
Sughrue Mion Zinn Macpeak & Seas, PLLC
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