Memory insensitive to disturbances

Details Memory insensitive to disturbances Memory insensitive to disturbances

1995-10-17

1996-10-29

Nelms, David C.

Static information storage and retrieval

Systems using particular element

Semiconductive

365181, 365206, 365227, G11C 1134, G11C 702

Patent

active

055703135

ABSTRACT:
The invention concerns a memory cell insensitive to disturbances. The memory cell, that contains information in the form of two complementary logical levels (X, C(X)), each logical level being stored in a node of the cell (N1, N2), is characterized in that it comprises means of storing the same logical level in two different nodes (N1, N2, N3, N4), the said means being able to restore any logical level to its initial state preceding a modification made on it due to a disturbance, as a result of holding the value of one of the two logical levels complementary to the logical level that was modified.

REFERENCES:
patent: 5157625 (1992-10-01), Barry
patent: 5410507 (1995-04-01), Tazunoki et al.
IBM Technical Disclosure Bulletin, Twice Redundant Radiation Hardened Latch, vol. 30, No. 8, Jan. 1988, pp. 248-249.
Kerns, Sherra E., The Design of Radiation-Hardened ICs for Space: A Compendium of Approaches, Proceedings of the IEEE, Nov. 1988, pp. 1470-1509.
Diehl, S. E. and Vinson, J. E., Consideration for Single Event Immune VLSI Logic, IEEE Transactions on Nuclear Science, vol. 30, No. 6, Dec. 1983, pp. 4501-4507.
U.S. Ser. No. 08/099,656 Jul. 30, 1993 abandoned.
U.S. Ser. No. 08/274,142 Jul. 14, 1994 5,410,506 Apr. 25, 1995.
U.S. Ser. No. 08/201,034 Feb. 24, 1994 5,469,485 Nov. 21, 1995.

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