Electrical computers and digital data processing systems: input/ – Input/output data processing – Peripheral configuration
Patent
1997-12-16
2000-02-22
Lee, Thomas C.
Electrical computers and digital data processing systems: input/
Input/output data processing
Peripheral configuration
710 19, 710 51, 711156, 711163, 711166, G06F 1310, G06F 1316, G06F 124, G06F 1200
Patent
active
060292105
ABSTRACT:
When normal data is written to a desired address in a DRAM, a guarantee bit comparing/generating circuit sets the value of guarantee bit data stored at the address corresponding to the desired address in a DRAM as a value indicating that the normal data has been written. Since the guarantee bit data stored at each address in the DRAM always becomes "000" or "111" immediately after power is turned on, the above described value indicating that the normal data has been written is set as a value other than "000" and "111". Thereafter, if the value of the guarantee bit data stored at the address corresponding to the desired address in the DRAM indicates that the normal data has been written when the normal data is read from the desired address in the DRAM, the normal data read from the DRAM is output to a data bus. Otherwise, the fixed value "0" is output to the data bus as read data.
REFERENCES:
patent: 4720819 (1988-01-01), Pinkham et al.
patent: 5638536 (1997-06-01), Nakai et al.
patent: 5777999 (1998-07-01), Hiraki et al.
Fujitsu Limited
Lee Thomas C.
Park Ilwoo
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