Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
Patent
1997-11-14
2000-02-29
Bragdon, Reginald G.
Electrical computers and digital processing systems: memory
Storage accessing and control
Control technique
711166, G06F 1200
Patent
active
060322357
ABSTRACT:
A memory initialization circuit for preventing random garbage data left over from a previous program from being read into a newly executed program. The initialization circuit is applicable to memories of all types, but is particularly useful for memories used to implement audio effects through the use of audio delay lines and audio tables. The memory initialization circuit includes multiple dual-use memory buffers, each of which store data for either a value representative of an audio delay length or an audio data signal. Multiple memory use indicators (e.g., flags) corresponding to the dual-use memory buffers indicate whether the data stored in each buffer represents an audio delay length or an audio data signal. The circuit also includes a counter that sequentially updates a count value and compare logic, which is coupled to the dual-use memory buffers and to the counter. The compare logic updates a given memory use indicator based on a comparison of the data stored in the memory buffer corresponding to the given memory use indicator and the value of the counter. When the counter reaches a stored audio delay length value, the memory use indicator is reset to a state that indicates valid TRAM data can be loaded into the memory buffer location. The circuit requires only one counter for the entire array of memory buffer locations.
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Bragdon Reginald G.
Creative Technology Ltd.
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