Memory in logic cell

Static information storage and retrieval – Floating gate – Particular connection

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C365S185180, C365S185270

Reexamination Certificate

active

07633801

ABSTRACT:
Methods, devices, and systems for a memory in logic cell are provided. One or more embodiments include using a cell structure having a first gate, a second gate, and a third gate, e.g., a control gate, a back gate, and a floating gate, as a memory in logic cell. The method includes programming the floating gate to a first state to cause the memory in logic cell to operate as a first logic gate type. The method further includes programming the floating gate to a second state to cause the memory in logic cell to operate as a second logic gate type.

REFERENCES:
patent: 5991225 (1999-11-01), Forbes et al.
patent: 6124729 (2000-09-01), Noble et al.
patent: 6153486 (2000-11-01), Forbes et al.
patent: 6208164 (2001-03-01), Noble et al.
patent: 6351428 (2002-02-01), Forbes
patent: 6384448 (2002-05-01), Forbes
patent: 6445032 (2002-09-01), Kumar et al.
patent: 6486027 (2002-11-01), Noble et al.
patent: 6635923 (2003-10-01), Hanafi et al.
patent: 6812516 (2004-11-01), Noble et al.
patent: 7089515 (2005-08-01), Hanafi et al.
patent: 7129749 (2006-10-01), Fenstermaker et al.
patent: 7187587 (2007-03-01), Forbes
patent: 7402850 (2008-07-01), Bhattacharyya
patent: 2003/0043637 (2003-03-01), Forbes et al.
patent: 2003/0048666 (2003-03-01), Eldridge et al.
patent: 2005/0024945 (2005-02-01), Forbes
patent: 2006/0002192 (2006-01-01), Forbes et al.
patent: 2006/0284236 (2006-12-01), Bhattacharyya
patent: 2007/0012988 (2007-01-01), Bhattacharyya
patent: 2007/0064494 (2007-03-01), Morton et al.
Avei, U., et al., “Back-gated MOSFETs with controlled silicon thinckness for adaptive threshold-voltage control”, Electronics Letters, vol. 40, No. 1 (Jan. 8, 2004).
Drude, Paul, “Technology Research News”, Nature, Institut Fur Feskorperelektronik, (1 pg.) (Oct. 2, 2003).
Hanyu, T., et al., “Multiple-Valued Logic-in-Memory VLSI . . .”, IEEE Int. Solid State Circuits Conference, Dig. Tech. papers, pp. 194-195, (Feb. 1998).
Kautz, William H., “Cellular Logic-in-Memory Arrays”, IEEE Transactions on Computers. vol. C-18, No. 8 (Aug. 1969).
Lin, Hao, et al., “Super-Self-Aligned Back-Gate/Double-Gate Planar Transistors . . .”, Device Research Conference, Tech. Digest, pp. 37-38 (Jun. 2006).
Ney, A., et al., “Programmable computing with a single magnetoresistive element”, Nature, vol. 425, pp. 485-487 (Oct. 2, 2003).
Tanaka, Tetsu, et al., “Analysis of P+ Poly Si Double-Gate Thin-File SOI MOSFETS”, IEDM Technology Digest, pp. 683-686 (1991).

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Memory in logic cell does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Memory in logic cell, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory in logic cell will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-4131704

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.